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Diffstat (limited to 'results/classifier/108/other/1480562')
| -rw-r--r-- | results/classifier/108/other/1480562 | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/results/classifier/108/other/1480562 b/results/classifier/108/other/1480562 new file mode 100644 index 000000000..1fad6269d --- /dev/null +++ b/results/classifier/108/other/1480562 @@ -0,0 +1,68 @@ +device: 0.695 +semantic: 0.675 +socket: 0.667 +performance: 0.664 +network: 0.599 +PID: 0.541 +permissions: 0.540 +vnc: 0.522 +boot: 0.513 +graphic: 0.502 +KVM: 0.469 +debug: 0.457 +files: 0.449 +other: 0.436 + +register values in sp804 timer + +In the arm_timer.c, when first reading the load register, I got 0. + +... +case 0: /* TimerLoad */ +... + +According to the specification at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html, +"The minimum valid value for TimerXLoad is 1". Is the initial value supposed to be 0xffffffff? + + +When the 5th and 7th bit in Control Register are set, RIS and MIS remain 0. But should they be enabled (i.e., 0x1 and 0x1) as both interrupt and timer module are set. + +Thanks. + +On 1 August 2015 at 15:46, T-T Yu <email address hidden> wrote: +> Public bug reported: +> +> In the arm_timer.c, when first reading the load register, I got 0. +> +> ... +> case 0: /* TimerLoad */ +> ... +> +> According to the specification at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html, +> "The minimum valid value for TimerXLoad is 1". Is the initial value +> supposed to be 0xffffffff? + +No. See the "summary of registers" table 3.1 in section 3.1, +which lists this register's reset value as zero (and also +section 2.2.6 which agrees that on reset the load register +value is zero). + +The text you quote is attempting to describe the minimum +value which it is sensible to write to the register -- it +makes no sense for an OS to write 0 to this register because +it would always just interrupt immediately with no actual +timer function, so the shortest possible timeout is +obtained by writing a 1. + +> When the 5th and 7th bit in Control Register are set, RIS and MIS +> remain 0. But should they be enabled (i.e., 0x1 and 0x1) as both +> interrupt and timer module are set. + +RIS and MIS will only become 1 when the timer generates an +interrupt. They don't get set merely because the OS has +enabled interrupts. + +thanks +-- PMM + + |