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+performance: 0.889
+device: 0.856
+graphic: 0.799
+network: 0.740
+semantic: 0.601
+socket: 0.553
+permissions: 0.531
+debug: 0.483
+boot: 0.446
+vnc: 0.428
+PID: 0.356
+KVM: 0.310
+other: 0.308
+files: 0.183
+
+intel-hda:  SD_STS different behavior for byte write vs. word write
+Description of problem:
+The Intel HDA SD_STS register is accessible two different ways in QEMU:  either it's the top 8 bits of a 32-bit access
+or it's directly accessible as a byte.
+On reads, the register behavior for SD_STS is identical whether accessed as a 32-bit read or an 8-bit read.
+On writes, the behavior is different; when written to as an 8-bit write, the BCIS, FIFOE, and DESE bits implement the documented HDA behavior of RW1C (writing a 1 to a bit clears it).  When written to as the top 8 bits of a 32-bit write, writing a 1 to a bit sets the bit -- so an attempt to clear a status bit instead unconditionally sets the status bit.
+Steps to reproduce:
+1.  Write 32 bits at SD_CTL address with bit 27 set (FIFOE).  This should clear FIFOE, but does not.
+2.  Read back SD_STS (SD_CTL address + 3) as a byte.  The FIFOE bit will be set.
+3.  Write 8 bits at SD_STS address with bit 3 set (FIFOE).  This should clear FIFOE, and it does.
+4.  Read back SD_STS as a byte.  The FIFOE bit will be cleared.
+Additional information:
+