1 files changed, 73 insertions, 0 deletions
diff --git a/results/classifier/118/architecture-arm/1843254 b/results/classifier/118/architecture-arm/1843254
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+++ b/results/classifier/118/architecture-arm/1843254
@@ -0,0 +1,73 @@
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+--------------------
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+
+arm emulation of HCR.TID3 traps are not implemented
+
+On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3, which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers. However, setting that HCR bit has no effect and accesses to those ID registers are not trapped to EL2 with an EC syndrome value of 0x18.
+
+Yes, we don't currently implement most of the 'trap system register access' bits in HCR_EL2. Last time I checked we were missing TID0 TID1 TID2 TID3 TIDCP TAC TSW TPC TPU TTLB TVM TRVM TDZ, but it's possible we've implemented one or two of those since then.
+
+
+TID3 trapping should be mostly fixed for 4.2 -- we will trap accesses to all the coprocessor/sysreg ID registers that TID3 covers. Trapping of aarch32 MVFR* (which are accessed via vmrs) will not make it into this release, but should be in 5.0.
+
+
+The last bit of TID3 trapping is now in QEMU git master and will be in 5.0.
+
+