1 files changed, 98 insertions, 0 deletions
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+++ b/results/classifier/118/architecture-risc-v/1923629
@@ -0,0 +1,98 @@
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+--------------------
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+
+RISC-V Vector Instruction vssub.vv not saturating
+
+I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF).
+
+Here is the bit of the code:
+
+		vmv.v.i		v16, 0
+		…
+8f040457	vssub.vv	v8,v16,v8
+
+I believe the instruction encoding is correct (vssub.vv with vd = v8, vs2 = v16, rs1 = v8), but the result does not saturate in QEMU.
+
+I’ve just tested with what I think is the latest branch ( https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb 2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still exists.
+
+Thanks for raising this bug case. A fix should be available soon.
+
+This should be a quick fix, we will run couple tests again to ensure the fix doesn't break anything. Thanks~
+
+This was fixed by commit:
+
+commit 65606f21243a796537bfe4708720a9bf4bb50169
+Author: LIU Zhiwei <email address hidden>
+Date:   Fri Feb 12 23:02:21 2021 +0800
+
+    target/riscv: Fixup saturate subtract function
+    
+    The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
+    However, when the predication is ture and a is 0, it should return maximum.
+    
+    Signed-off-by: LIU Zhiwei <email address hidden>
+    Reviewed-by: Richard Henderson <email address hidden>
+    Reviewed-by: Alistair Francis <email address hidden>
+    Message-id: <email address hidden>
+    Signed-off-by: Alistair Francis <email address hidden>
+
+
+The fix will be in the QEMU 6.1 release.
+