diff options
Diffstat (limited to 'results/classifier/118/mistranslation-arm/1417')
| -rw-r--r-- | results/classifier/118/mistranslation-arm/1417 | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/results/classifier/118/mistranslation-arm/1417 b/results/classifier/118/mistranslation-arm/1417 new file mode 100644 index 000000000..b86e46d44 --- /dev/null +++ b/results/classifier/118/mistranslation-arm/1417 @@ -0,0 +1,65 @@ +arm: 0.953 +mistranslation: 0.945 +semantic: 0.933 +device: 0.903 +architecture: 0.899 +ppc: 0.878 +graphic: 0.852 +socket: 0.768 +network: 0.737 +risc-v: 0.706 +PID: 0.704 +vnc: 0.699 +performance: 0.649 +debug: 0.634 +register: 0.607 +VMM: 0.564 +kernel: 0.560 +assembly: 0.540 +TCG: 0.493 +files: 0.444 +peripherals: 0.407 +permissions: 0.390 +boot: 0.375 +x86: 0.331 +hypervisor: 0.257 +user-level: 0.223 +i386: 0.147 +virtual: 0.140 +KVM: 0.053 +-------------------- +arm: 0.997 +debug: 0.593 +performance: 0.483 +TCG: 0.104 +architecture: 0.054 +hypervisor: 0.051 +files: 0.039 +PID: 0.022 +kernel: 0.017 +user-level: 0.016 +register: 0.016 +device: 0.013 +virtual: 0.013 +semantic: 0.010 +assembly: 0.008 +risc-v: 0.007 +vnc: 0.005 +peripherals: 0.005 +network: 0.003 +permissions: 0.002 +VMM: 0.002 +boot: 0.001 +socket: 0.001 +mistranslation: 0.001 +graphic: 0.001 +ppc: 0.000 +x86: 0.000 +KVM: 0.000 +i386: 0.000 + +QEMU fails an assertion when hitting a breakpoint that is set on a tlb-missed 2-stage translated AArch64 memory +Description of problem: +After upgrading to QEMU v7.2.0 from v7.1.0, when hitting an instruction breakpoint on a memory address that is translated by 2 stages of translation, and is not already cached in the TLB, QEMU fails the assertion at target/arm/ptw.c:301 (`assert(fi->type != ARMFault_None);`). + +I believe this was introduced in f3639a64f602ea5c1436eb9c9b89f42028e3a4a8 (@rth7680), since in that commit the failure check for the return value of `get_phys_addr_lpae()` changed from checking for true (meaning failure) to checking for false (which actually means success). |