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+PID: 0.234
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+i386: 0.204
+kernel: 0.200
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+TCG: 0.155
+x86: 0.153
+mistranslation: 0.148
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+
+[riscv/regression] Missing tlb flush introduced in refactoring
+
+Hello,
+
+In qemu-system-riscv64, following a QEMU update, I get all sort of weird and not easily reproducible crashes in my risc-v guest.
+
+I have bissected this issue to commit c7b951718815694284501ed01fec7acb8654db7b.
+Some TLB flushes were removed in the following places:
+target/riscv/cpu_helper.c: `csr_write_helper(env, s, CSR_MSTATUS);` -> `env->mstatus = s;` (twice)
+target/riscv/op_helper.c: `csr_write_helper(env, s, CSR_MSTATUS);` -> `env->mstatus = s;` (twice)
+
+Adding TLB flushes in all 4 places fixes the issues for me.
+
+Hello,
+
+Thanks for reporting a bug.
+
+Can you please include details to reproduce the problems that you are seeing? This includes images and command line arguments.
+
+Do you also mind including the diff of what fixes the problem for you?
+
+Alistair
+
+It has been solved thanks to the mailing-list members.
+