1 files changed, 43 insertions, 0 deletions
diff --git a/results/classifier/118/none/1889288 b/results/classifier/118/none/1889288
new file mode 100644
index 000000000..2a719860b
--- /dev/null
+++ b/results/classifier/118/none/1889288
@@ -0,0 +1,43 @@
+mistranslation: 0.724
+arm: 0.706
+architecture: 0.681
+semantic: 0.599
+graphic: 0.519
+assembly: 0.467
+device: 0.440
+permissions: 0.408
+socket: 0.381
+performance: 0.356
+vnc: 0.348
+network: 0.348
+ppc: 0.335
+kernel: 0.310
+files: 0.300
+debug: 0.270
+user-level: 0.264
+register: 0.236
+x86: 0.232
+virtual: 0.219
+peripherals: 0.210
+PID: 0.200
+risc-v: 0.195
+i386: 0.185
+boot: 0.182
+VMM: 0.166
+TCG: 0.147
+KVM: 0.137
+hypervisor: 0.132
+
+aarch64 BICS instruciton doesn't set flags
+
+When reading the source for translate-a64.c here:
+
+https://github.com/qemu/qemu/blob/a466dd084f51cdc9da2e99361f674f98d7218559/target/arm/translate-a64.c#L4783
+
+I noticed that it does not appear to call gen_logic_CC for the BICS instruction so is not setting the flags as required. I haven't tried to produce a test case for it but it seems like it might be a bug.
+
+The code is correct (though it is admittedly not entirely obvious at first glance). The switch statement at line 4753 is on "(opc | (invert << 2))" (where opc is a 2 bit field and invert a 1 bit field). Both ANDS and BICS have opc==3 and so will cause a call to gen_logic_CC(). The difference between the two insns is that ANDC has invert==0 and BICS has invert==1.
+
+
+Oh yes I see. Sorry for the false report.
+