diff options
Diffstat (limited to 'results/classifier/accel-gemma3:12b/tcg/1863247')
| -rw-r--r-- | results/classifier/accel-gemma3:12b/tcg/1863247 | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/results/classifier/accel-gemma3:12b/tcg/1863247 b/results/classifier/accel-gemma3:12b/tcg/1863247 new file mode 100644 index 000000000..7bb480bfd --- /dev/null +++ b/results/classifier/accel-gemma3:12b/tcg/1863247 @@ -0,0 +1,9 @@ + +AArch64 EXT instruction for V register does not clear MSB side bits + +On AArch64 CPU with SVE register, there seems to be a bug in the operation when executing EXT instruction to V registers. Bits above the 128 bits of the SVE register must be cleared to 0, but qemu-aarch64 seems to hold the value. + +Example +ext v0.16b, v1.16b v2.16b, 8 + +After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width. \ No newline at end of file |