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diff --git a/results/classifier/deepseek-1/output/hypervisor/608107 b/results/classifier/deepseek-1/output/hypervisor/608107
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-
-ppc fails to clear MSR_POW when incurring exception
-
-QEMU VERSION: 0.12.4
-
-According to FreeScale's 'Programming Environments Manual for 32-bit Implementations of the PowerPC Architecture' [MPCFPE32B, Rev.3, 9/2005], section 6.5, table 6-7, an interrupt resets MSR_POW to zero but qemu-0.12.4 fails to do so.
-Resetting the bit is necessary in order to bring the processor out of power-management since otherwise it goes to sleep right away in the exception handler, i.e., it is impossible to leave PM-mode.
-
-
-
-Thomas Monjalon wrote:
-> From: till <email address hidden>
->
-> According to FreeScale's 'Programming Environments Manual for 32-bit
-> Implementations of the PowerPC Architecture' [MPCFPE32B, Rev.3, 9/2005],
-> section 6.5, table 6-7, an interrupt resets MSR_POW to zero but qemu-0.12.4
-> fails to do so.
-> Resetting the bit is necessary in order to bring the processor out of power
-> management since otherwise it goes to sleep right away in the exception
-> handler, i.e., it is impossible to leave PM-mode.
->   
-
-This doesn't look right. POW shouldn't even get stored in SRR1. Could
-you please redo the patch and make sure that mtmsr masks out MSR_POW?
-
-
-Alex
-
-
-I'm afraid I don't understand. My the problem and fix doesn't address mtmsr at all.
-It just makes sure MSR_POW is cleared in MSR when an exception occurs.
-
-Do you mean MSR_POW should masked from MSR before saving it to SRR1?
-That's already taken care of (target-ppc/helper.c:2074 [qemu-0.12.4]).
-
-As far as I can see, this problem has been fixed by this commit here:
-http://git.qemu.org/?p=qemu.git;a=commitdiff;h=41557447d30eeb944e4
-... so I'm setting the status to "Fix released" now.
-