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Diffstat (limited to 'results/scraper/box64/2007')
| -rw-r--r-- | results/scraper/box64/2007 | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/results/scraper/box64/2007 b/results/scraper/box64/2007 new file mode 100644 index 000000000..7e7515883 --- /dev/null +++ b/results/scraper/box64/2007 @@ -0,0 +1,8 @@ +[RV64_DYNAREC] How to View Register Values at Runtime and Set Breakpoints in RISC-V Target Code? +I'm currently trying to modify the translation logic of some RISC-V instructions, but I encounter errors in the computation results when running test programs. To diagnose the issue, I’d like to observe the state of RISC-V registers at a specific point during execution. I have the following questions: + +1. How can I view the RISC-V register values of the translated target code at a specific moment during runtime? +2. Is it possible to set breakpoints in the RISC-V target code, so I can pause execution midway and facilitate debugging? + +I'm looking for straightforward methods (e.g., using debugging tools) to accomplish this or any recommended techniques to check the real-time state of registers. + |