From 05ed9b00104b3da2e9cb0d541b5c5bbceb027fde Mon Sep 17 00:00:00 2001 From: Christian Krinitsin Date: Sun, 1 Jun 2025 21:19:28 +0200 Subject: adjust classifier --- .../semantic_issues/gitlab_semantic_addsubps | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 classification/semantic_issues/gitlab_semantic_addsubps (limited to 'classification/semantic_issues/gitlab_semantic_addsubps') diff --git a/classification/semantic_issues/gitlab_semantic_addsubps b/classification/semantic_issues/gitlab_semantic_addsubps new file mode 100644 index 000000000..60438ff08 --- /dev/null +++ b/classification/semantic_issues/gitlab_semantic_addsubps @@ -0,0 +1,23 @@ +x86 SSE/SSE2/SSE3 instruction semantic bugs with NaN + +Description of problem +The result of SSE/SSE2/SSE3 instructions with NaN is different from the CPU. From Intel manual Volume 1 Appendix D.4.2.2, they defined the behavior of such instructions with NaN. But I think QEMU did not implement this semantic exactly because the byte result is different. + +Steps to reproduce + +Compile this code + +void main() { + asm("mov rax, 0x000000007fffffff; push rax; mov rax, 0x00000000ffffffff; push rax; movdqu XMM1, [rsp];"); + asm("mov rax, 0x2e711de7aa46af1a; push rax; mov rax, 0x7fffffff7fffffff; push rax; movdqu XMM2, [rsp];"); + asm("addsubps xmm1, xmm2"); +} + +Execute and compare the result with the CPU. This problem happens with other SSE/SSE2/SSE3 instructions specified in the manual, Volume 1 Appendix D.4.2.2. + +CPU xmm1[3] = 0xffffffff + +QEMU xmm1[3] = 0x7fffffff + +Additional information +This bug is discovered by research conducted by KAIST SoftSec. -- cgit 1.4.1