From 9260319e7411ff8281700a532caa436f40120ec4 Mon Sep 17 00:00:00 2001 From: Christian Krinitsin Date: Fri, 30 May 2025 16:52:07 +0200 Subject: gitlab scraper: download in toml and text format --- .../target_i386/host_missing/accel_missing/1164 | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 gitlab/issues_text/target_i386/host_missing/accel_missing/1164 (limited to 'gitlab/issues_text/target_i386/host_missing/accel_missing/1164') diff --git a/gitlab/issues_text/target_i386/host_missing/accel_missing/1164 b/gitlab/issues_text/target_i386/host_missing/accel_missing/1164 new file mode 100644 index 000000000..d79ec6483 --- /dev/null +++ b/gitlab/issues_text/target_i386/host_missing/accel_missing/1164 @@ -0,0 +1,17 @@ +q35: incorrect values for PCIEXBAR masks +Description of problem: +https://lore.kernel.org/all/1fded151ce5ecbf7010427871b908000b2aba9ee.1520867956.git.x1917x@gmail.com/ + +In function [mch_update_pciexbar](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/pci-host/q35.c#L295) + +There are two small issues in PCIEXBAR address mask handling: +- wrong bit positions for address mask bits (see PCIEXBAR description + in Q35 datasheet) +- incorrect usage of 64ADR_MASK + +Due to this, attempting to write a valid PCIEXBAR address may cause it to +shift to another address, causing memory layout corruption where emulated +MMIO regions may overlap real (passed through) MMIO ranges. Fix this +by providing correct values. +Additional information: +Q35 datasheet: https://www.intel.com/Assets/PDF/datasheet/316966.pdf ( 5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ) -- cgit 1.4.1