From 3e4c5a6261770bced301b5e74233e7866166ea5b Mon Sep 17 00:00:00 2001 From: Christian Krinitsin Date: Sun, 1 Jun 2025 21:35:14 +0200 Subject: clean up repository --- .../target_missing/host_missing/accel_missing/2550 | 25 ---------------------- 1 file changed, 25 deletions(-) delete mode 100644 gitlab/issues_text/target_missing/host_missing/accel_missing/2550 (limited to 'gitlab/issues_text/target_missing/host_missing/accel_missing/2550') diff --git a/gitlab/issues_text/target_missing/host_missing/accel_missing/2550 b/gitlab/issues_text/target_missing/host_missing/accel_missing/2550 deleted file mode 100644 index e0925fdc2..000000000 --- a/gitlab/issues_text/target_missing/host_missing/accel_missing/2550 +++ /dev/null @@ -1,25 +0,0 @@ -GICv3 vGIC system registers not initialized on ARM Cortex-A15 -Description of problem: -For Cortex-A15, the GICv3 vGIC registers are not initialized like for AArch64 CPUs, for example Cotex-A35, Cortex-A55, etc -Steps to reproduce: -The setup is not trivial. I can provide a boot image on request. But I hope the problem is straight-forward. -Additional information: -Suggested fix: -```diff -index 20c2737f17..136b513bda 100644 ---- a/target/arm/tcg/cpu32.c -+++ b/target/arm/tcg/cpu32.c -@@ -569,6 +569,12 @@ static void cortex_a15_initfn(Object *obj) - cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ - cpu->isar.reset_pmcr_el0 = 0x410F3000; -+ -+ /* From B3.5 VGIC Type register */ -+ cpu->gic_num_lrs = 4; -+ cpu->gic_vpribits = 5; -+ cpu->gic_vprebits = 5; -+ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); - } - -``` -- cgit 1.4.1