id = 904
title = "RISC-V: Cannot set SEIP bit of mip csr register in M mode"
state = "closed"
created_at = "2022-03-12T08:49:54.479Z"
closed_at = "2022-04-22T10:54:01.743Z"
labels = ["target: riscv"]
url = "https://gitlab.com/qemu-project/qemu/-/issues/904"
host-os = "Ubuntu"
host-arch = "x86_64"
qemu-version = "6.1.1"
guest-os = "No operating system"
guest-arch = "riscv64 imafc, riscv32 imafc"
description = """"""
reproduce = """1.   run assembly instructions **in M mode**: 
```
not t0, x0    // set t0 to 0b11..11
csrs mip, t0  // write mip with t0, mip registers are WARL(Write Any Values, Reads Legal Values)
csrr t1, mip  // read value from mip to t1
```
2.   GDB enters the command `display/z $t1` to see that the content of the t1 register is 0x466, which means that the SEIP bit of mip is not set.
3.   According to page 47 of [riscv-privileged-20211203](https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf), `SEIP is writable in mip`.
4.   According to page 81 of the same manual,`If implemented, SEIP is read-only in sip`.
5.   However, the above code and results show that the SEIP bit of mip cannot be set by software **in M mode**."""
additional = """"""