Okay, I need to classify this bug report as either user-mode or system-mode related. The issue is about QEMU not setting mtval/stval correctly for illegal instructions in RISC-V. Let me think: When dealing with exceptions and traps in RISC-V, the handling involves both the CPU and the exception vectors. If a program triggers an illegal instruction, it's a trap that should be handled by the OS or the system's exception handler. In this case, the problem arises when running a user-space program that causes an illegal instruction. The trap handler is part of the kernel or OS, which operates at a higher privilege level (system mode). QEMU simulates both the CPU and the system environment, so if mtval isn't set correctly, it might be an issue in how QEMU handles system-level traps. The user mentions using GDB to debug and seeing that mtval is 0 instead of the expected instruction. This suggests that during exception handling, the registers aren't being updated properly. Since this involves the CPU's state and exception handling, which are part of the system's operation, it likely falls under system-mode. So, considering all this, I think the bug is related to system-mode. system