semantic: 0.599
graphic: 0.519
other: 0.455
device: 0.440
permissions: 0.408
socket: 0.381
performance: 0.356
vnc: 0.348
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files: 0.300
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PID: 0.200
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KVM: 0.137

aarch64 BICS instruciton doesn't set flags

When reading the source for translate-a64.c here:

https://github.com/qemu/qemu/blob/a466dd084f51cdc9da2e99361f674f98d7218559/target/arm/translate-a64.c#L4783

I noticed that it does not appear to call gen_logic_CC for the BICS instruction so is not setting the flags as required. I haven't tried to produce a test case for it but it seems like it might be a bug.

The code is correct (though it is admittedly not entirely obvious at first glance). The switch statement at line 4753 is on "(opc | (invert << 2))" (where opc is a 2 bit field and invert a 1 bit field). Both ANDS and BICS have opc==3 and so will cause a call to gen_logic_CC(). The difference between the two insns is that ANDC has invert==0 and BICS has invert==1.


Oh yes I see. Sorry for the false report.