mistranslation: 0.713 arm: 0.670 semantic: 0.575 architecture: 0.557 kernel: 0.545 device: 0.294 assembly: 0.255 socket: 0.171 register: 0.157 PID: 0.143 virtual: 0.140 x86: 0.140 peripherals: 0.127 graphic: 0.124 ppc: 0.120 performance: 0.116 permissions: 0.095 hypervisor: 0.091 debug: 0.087 vnc: 0.080 user-level: 0.076 risc-v: 0.073 network: 0.065 files: 0.064 boot: 0.058 VMM: 0.043 TCG: 0.032 i386: 0.029 KVM: 0.024 ARM: CORTEX M, PRIMASK does not disable interrupts qemu version 0.15.1 but the same code is in qemu 1.0 "CPSID I" does not disable interrupts for CORTEX M3 if (interrupt_request & CPU_INTERRUPT_HARD && ((IS_M(env) && env->regs[15] < 0xfffffff0) || !(env->uncached_cpsr & CPSR_I))) { env->exception_index = EXCP_IRQ; do_interrupt(env); next_tb = 0; } do_interrupt() will be executed even if (env->uncached_cpsr & CPSR_I) == 1 , disable interrupt bit set. then changed to: if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_cpsr & CPSR_I) && (IS_M(env) ? env->regs[15] < 0xfffffff0: 1) ) { env->exception_index = EXCP_IRQ; do_interrupt(env); next_tb = 0; } works This change changes the behaviour for non-M-profile cores, which looks wrong. See discussion in this mailing list thread where a similar patch was suggested: http://lists.gnu.org/archive/html/qemu-devel/2011-06/msg00500.html M profile interrupt handling is known-broken. I'm not accepting any patches in this area unless they come attached to a decent explanation of why they are the correct change to make and show some evidence of the whole problem having been considered. > This change changes the behaviour for non-M-profile cores ...or maybe not: I was confused by the resemblance to that other patch. I still think one-line fixes are unlikely to be the right approach here, though. This long-standing bug has been fixed by the rewrite of the M-profile exception handling for QEMU 2.9.