RISC-V PLIC enable interrupt for multicore

Hello all,

There is a bug in Qemu related to the enabling of external interrupts for multicores (Virt machine). 

After correcting Qemu as described in #1815078  (https://bugs.launchpad.net/qemu/+bug/1815078), when we try to enable interrupts for core 1 at address 0x0C00_2080 we don't seem to be able to trigger an external interrupt  (e.g. UART0).

This works perfectly for core 0, but fore core 1 it does not work at all. I assume that given bug #1815078 does not enable any external interrupt then this feature has not been tested. I tried to look at the qemu source code but with no luck so far.

I guess the problem is related to function parse_hart_config (in sfive_plic.c) that initializes incorrectly the plic->addr_config[addrid].hartid, which is later on read in sifive_plic_update. But this is a guess.

Best regards,
Pharos team