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RISC-V Vector Extension Seems Not Working Well
## Description
I encountered a weird bug when running `lstopo` (https://archlinux.org/packages/extra/x86_64/hwloc/) with box64 for _testing_. It raised `SIGILL` like this:
```
86920|SIGILL @0x7040b8b85618 (???(0x7040b8b85618)) (x64pc=0x3f020a7073/"/lib/libcairo.so.2 + 0xa7073", rsp=0x7040bb5fa390, stack=0x7040bae00000:0x7040bb600000 own=(nil) fp=0x7040bb5fae30), for accessing 0x7040b8b85618 (code=1/prot=7), db=0x7040b9dfef40(0x7040b8b84f80:0x7040b8b85b48/0x3f020a6f06:0x3f020a7103//lib/libcairo.so.2 + 0xa6f06:clean, hash:89047ac9/89047ac9) handler=(nil)
RAX:0x000000003744f690 RCX:0x0000000000000000 RDX:0x000000003732fa20 RBX:0x0000000037315650
RSP:0x00007040bb5fa390 RBP:0x00007040bb5fae48 RSI:0x0000000000000042 RDI:0x00007040bb5fa340
R8:0x00007040bb5fa440 R9:0x000000003732f830 R10:0x000000003744f6d0 R11:0x0000000000000000
R12:0x0000000000000001 R13:0x00000000374498d0 R14:0x000000003732fa20 R15:0x00007040bb5fa600
ES:0x002b CS:0x0033 SS:0x002b DS:0x002b FS:0x0043 GS:0x0053
RSP-0x20:0x00000000374497e0 RSP-0x18:0x000000003744ad90 RSP-0x10:0x00007040bb5fa600 RSP-0x08:0x0000003f020a6f06
RSP+0x00:0x0000000100000f00 RSP+0x08:0x000000003744f6d0 RSP+0x10:0x000000000000000d RSP+0x18:0x00007040bb5fae30 opcode=27 F5 05 02 27 38 05 0F (0F 84 B7 07 00)
[1] 86920 illegal hardware instruction (core dumped) ./box64 lstopo
```
I found that, if I turned off `rv64_vector` manually, this `SIGILL` would not occur. So it must be something wrong in box64 with `rv64_vector` enabled.
## Investigation
I did some investigation about this issue, and found that, if I disabled this translation via inserting `return 0` after `case 0x6C`, this bug would not occur.
https://github.com/ptitSeb/box64/blob/fc7f83c60b82e77712165dd600501af2c59b8d3b/src/dynarec/rv64/dynarec_rv64_660f_vector.c#L180-L203
Therefore, I think this instruction (`PUNPCKLQDQ`) is not processed correctly. However, GDB told me that illegal instruction did not come from this process, but from
https://github.com/ptitSeb/box64/blob/fc7f83c60b82e77712165dd600501af2c59b8d3b/src/dynarec/rv64/dynarec_rv64_helper.c#L1837
Weird...
## Want Help
I am not familiar with both x64 mmx and riscv vector extension, and failed to find out where the bug is in the past 2 days, so I am sending this issue and waiting for help/fix.
I checked the history of these code lines, and found PR #1755, #1811 & #1816 are related.
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