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| author | Cédric Le Goater <clg@kaod.org> | 2018-01-15 19:04:02 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-01-17 09:35:24 +1100 |
| commit | 09279d7e7b08ebfaaa40060843dbc8f33977548f (patch) | |
| tree | 32f5d6eae09c2ed7607e72aa3181d090a65ea683 | |
| parent | 83028a2b2871d3787e2fb55fe3e5cd2dda6cc378 (diff) | |
| download | focaccia-qemu-09279d7e7b08ebfaaa40060843dbc8f33977548f.tar.gz focaccia-qemu-09279d7e7b08ebfaaa40060843dbc8f33977548f.zip | |
ppc/pnv: change core mask for POWER9
When addressed by XSCOM, the first core has the 0x20 chiplet ID but the CPU PIR can start at 0x0. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | hw/ppc/pnv.c | 4 | ||||
| -rw-r--r-- | tests/pnv-xscom-test.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 536162b274..f9591cd41d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -707,9 +707,9 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) #define POWER8_CORE_MASK (0x7e7eull) /* - * POWER9 has 24 cores, ids starting at 0x20 + * POWER9 has 24 cores, ids starting at 0x0 */ -#define POWER9_CORE_MASK (0xffffff00000000ull) +#define POWER9_CORE_MASK (0xffffffffffffffull) static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) { diff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c index a1a119c091..9d545c4718 100644 --- a/tests/pnv-xscom-test.c +++ b/tests/pnv-xscom-test.c @@ -49,7 +49,7 @@ static const PnvChip pnv_chips[] = { .xscom_base = 0x000603fc00000000ull, .xscom_core_base = 0x0ull, .cfam_id = 0x220d104900008000ull, - .first_core = 0x20, + .first_core = 0x0, }, #endif }; |