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| author | Peter Maydell <peter.maydell@linaro.org> | 2025-09-25 12:57:23 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:32:21 +0100 |
| commit | a23e719ca8e80d22eafe4b2b57833918d439fa0c (patch) | |
| tree | 542aaf2b9d23aa19ca3775e2b9ad38bf2b9088b4 | |
| parent | eb7abb4a719f93ddd56571bf91681044b4159399 (diff) | |
| download | focaccia-qemu-a23e719ca8e80d22eafe4b2b57833918d439fa0c.tar.gz focaccia-qemu-a23e719ca8e80d22eafe4b2b57833918d439fa0c.zip | |
target/arm: Don't set HCR.RW for AArch32 only CPUs
In commit 39ec3fc0301 we fixed a bug where we were not implementing
HCR_EL2.RW as RAO/WI for CPUs where EL1 doesn't support AArch32.
However, we got the condition wrong, so we now set this bit even on
CPUs which have no AArch64 support at all. This is wrong because the
AArch32 HCR register defines this bit as RES0.
Correct the condition we use for forcing HCR_RW to be set.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3128
Fixes: 39ec3fc0301 ("target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250925115723.1293233-1-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/helper.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index aa730addf2..792a47a9c5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3742,7 +3742,8 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) value &= valid_mask; /* RW is RAO/WI if EL1 is AArch64 only */ - if (!cpu_isar_feature(aa64_aa32_el1, cpu)) { + if (arm_feature(env, ARM_FEATURE_AARCH64) && + !cpu_isar_feature(aa64_aa32_el1, cpu)) { value |= HCR_RW; } |