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| author | Cédric Le Goater <clg@kaod.org> | 2024-07-17 08:30:17 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2024-07-21 07:46:38 +0200 |
| commit | cc8bae6f6270c52c8f9854a83f9cefec3e5ec108 (patch) | |
| tree | 1838cf370128bca11eb574d215d6726a42f767ae | |
| parent | 255aed8134190966d0bd090c97391f6512c2fbc6 (diff) | |
| download | focaccia-qemu-cc8bae6f6270c52c8f9854a83f9cefec3e5ec108.tar.gz focaccia-qemu-cc8bae6f6270c52c8f9854a83f9cefec3e5ec108.zip | |
aspeed/scu: Add boot-from-eMMC HW strapping bit for AST2600 SoC
Bit SCU500[2] of the AST2600 controls the boot device of the SoC. Future changes will configure this bit to boot from eMMC disk images specially built for this purpose. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| -rw-r--r-- | include/hw/misc/aspeed_scu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 58db28db45..356be95e45 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -349,6 +349,10 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); #define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24) #define SCU_AST2600_H_PLL_OFF (0x1 << 23) +/* STRAP1 SCU500 */ +#define SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC (0x1 << 2) +#define SCU_AST2600_HW_STRAP_BOOT_SRC_SPI (0x0 << 2) + /* * SCU310 Clock Selection Register Set 4 (for Aspeed AST1030 SOC) * |