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| author | Michael Walle <michael@walle.cc> | 2011-03-07 23:00:13 +0100 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2011-03-31 08:54:05 +0200 |
| commit | fcda98630b121a63c9de0705df02e59f4dc2fecc (patch) | |
| tree | 9852e155b5db98e5346fb950b5ce6fc42f35b9ff | |
| parent | 4d54ec7898bd951007cb6122d5315584bd41d0c4 (diff) | |
| download | focaccia-qemu-fcda98630b121a63c9de0705df02e59f4dc2fecc.tar.gz focaccia-qemu-fcda98630b121a63c9de0705df02e59f4dc2fecc.zip | |
lm32: rename raise opcode to scall
To be consistent with the new reference manual. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
| -rw-r--r-- | target-lm32/lm32-decode.h | 2 | ||||
| -rw-r--r-- | target-lm32/translate.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/target-lm32/lm32-decode.h b/target-lm32/lm32-decode.h index f745b39626..42205d931e 100644 --- a/target-lm32/lm32-decode.h +++ b/target-lm32/lm32-decode.h @@ -60,7 +60,7 @@ #define DEC_NOR {B8(00000001), B8(00011111)} #define DEC_OR {B8(00001110), B8(00011111)} #define DEC_ORHI {B8(00011110), B8(00111111)} -#define DEC_RAISE {B8(00101011), B8(00111111)} +#define DEC_SCALL {B8(00101011), B8(00111111)} #define DEC_RCSR {B8(00100100), B8(00111111)} #define DEC_SB {B8(00001100), B8(00111111)} #define DEC_SEXTB {B8(00101100), B8(00111111)} diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 0b0e405fe7..aa08a142e2 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -583,7 +583,7 @@ static void dec_orhi(DisasContext *dc) tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16)); } -static void dec_raise(DisasContext *dc) +static void dec_scall(DisasContext *dc) { TCGv t0; int l1; @@ -1002,7 +1002,7 @@ static const DecoderInfo decinfo[] = { {DEC_NOR, dec_nor}, {DEC_OR, dec_or}, {DEC_ORHI, dec_orhi}, - {DEC_RAISE, dec_raise}, + {DEC_SCALL, dec_scall}, {DEC_RCSR, dec_rcsr}, {DEC_SB, dec_sb}, {DEC_SEXTB, dec_sextb}, |