Jitter: add support for SystemV syscall convention (arml / x86_64)

2 files changed, 16 insertions, 0 deletions

diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py
index 2b5dc4cf..267bcea6 100644
--- a/miasm2/arch/arm/jit.py
+++ b/miasm2/arch/arm/jit.py
@@ -106,6 +106,14 @@ class jitter_arml(Jitter):
     func_prepare_systemv = func_prepare_stdcall
     get_arg_n_systemv = get_arg_n_stdcall
 
+    def syscall_args_systemv(self, n_args):
+        args = [self.cpu.R0, self.cpu.R1, self.cpu.R2, self.cpu.R3,
+            self.cpu.R4, self.cpu.R5][:n_args]
+        return args
+
+    def syscall_ret_systemv(self, value):
+        self.cpu.R0 = value
+
     def init_run(self, *args, **kwargs):
         Jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py
index bf74051d..3322e722 100644
--- a/miasm2/arch/x86/jit.py
+++ b/miasm2/arch/x86/jit.py
@@ -272,3 +272,11 @@ class jitter_x86_64(Jitter):
         remaining_args = args[len(args_regs):]
         for arg in reversed(remaining_args):
             self.push_uint64_t(arg)
+
+    def syscall_args_systemv(self, n_args):
+        args = [self.cpu.RDI, self.cpu.RSI, self.cpu.RDX, self.cpu.R10,
+                self.cpu.R8, self.cpu.R9][:n_args]
+        return args
+
+    def syscall_ret_systemv(self, value):
+        self.cpu.RAX = value