ARM: add mnemonics

3 files changed, 43 insertions, 1 deletions

diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index d4b7d05a..b08d7940 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -2378,13 +2378,17 @@ armtop("svc", [bs('11011111'),  imm8])
 armtop("b", [bs('11100'),  offs11])
 armtop("und", [bs('1101'), bs('1110'), imm8_d1])
 
-armtop("rev",  [bs('10111010'), bs('00'), rsl, rdl], [rdl, rsl])
+armtop("rev",    [bs('10111010'), bs('00'), rsl, rdl], [rdl, rsl])
+armtop("rev16",  [bs('10111010'), bs('01'), rsl, rdl], [rdl, rsl])
 
 armtop("uxtb", [bs('10110010'), bs('11'), rml, rdl], [rdl, rml])
 armtop("uxth", [bs('10110010'), bs('10'), rml, rdl], [rdl, rml])
 armtop("sxtb", [bs('10110010'), bs('01'), rml, rdl], [rdl, rml])
 armtop("sxth", [bs('10110010'), bs('00'), rml, rdl], [rdl, rml])
 
+armtop("uxtab", [bs('111110100'), bs('101'), rn_nopc, bs('1111'), rd, bs('10'), rot2, rm_rot2], [rd, rn_nopc, rm_rot2])
+armtop("uxtah", [bs('111110100'), bs('001'), rn_nopc, bs('1111'), rd, bs('10'), rot2, rm_rot2], [rd, rn_nopc, rm_rot2])
+
 # thumb2 ######################
 #
 # ARM Architecture Reference Manual Thumb-2 Supplement
@@ -2768,6 +2772,7 @@ imm5_2 = bs(l=2, fname="imm5_2")
 imm_stype = bs(l=2, fname="stype")
 
 imm_stype_00 = bs('00', fname="stype")
+imm_stype_01 = bs('01', fname="stype")
 imm_stype_11 = bs('11', fname="stype")
 
 
@@ -3207,6 +3212,7 @@ armtop("rsb", [bs('11101011110'), scc, rn, bs('0'), imm5_3, rd, imm5_2, imm_styp
 armtop("orn", [bs('11101010011'), scc, rn_nopc, bs('0'), imm5_3, rd, imm5_2, imm_stype, rm_sh], [rd, rn_nopc, rm_sh] )
 # lsl
 armtop("mov", [bs('11101010010'), scc, bs('1111'), bs('0'), imm5_3, rd_nosppc, imm5_2, imm_stype_00, rm_sh], [rd_nosppc, rm_sh] )
+armtop("mov", [bs('11101010010'), scc, bs('1111'), bs('0'), imm5_3, rd_nosppc, imm5_2, imm_stype_01, rm_sh], [rd_nosppc, rm_sh] )
 armtop("mov", [bs('11101010010'), scc, bs('1111'), bs('0'), imm5_3, rd_nosppc, imm5_2, imm_stype_11, rm_sh], [rd_nosppc, rm_sh] )
 
 
@@ -3219,6 +3225,8 @@ armtop("eor", [bs('11110'), imm12_1, bs('00100'), scc, rn, bs('0'), imm12_3, rd_
 armtop("add", [bs('11110'), imm12_1, bs('10000'), scc, rn_nosppc, bs('0'), imm12_3, rd, imm12_8_t4], [rd, rn_nosppc, imm12_8_t4])
 armtop("cmp", [bs('11110'), imm12_1, bs('01101'), bs('1'), rn, bs('0'), imm12_3, bs('1111'), imm12_8] )
 
+armtop("cmp", [bs('11101011101'), bs('1'), rn, bs('0'), imm5_3, bs('1111'), imm5_2, imm_stype, rm_sh], [rn, rm_sh] )
+
 
 armtop("mvn", [bs('11110'), imm12_1, bs('00011'), scc, bs('1111'), bs('0'), imm12_3, rd, imm12_8])
 armtop("rsb", [bs('11110'), imm12_1, bs('01110'), scc, rn_nosppc, bs('0'), imm12_3, rd, imm12_8], [rd, rn_nosppc, imm12_8])
@@ -3277,3 +3285,5 @@ armtop("clz",  [bs('111110101011'), rm, bs('1111'), rd, bs('1000'), rm_cp], [rd,
 armtop("tbb",  [bs('111010001101'), rn_noarg, bs('11110000000'), bs('0'), bs_deref_reg_reg], [bs_deref_reg_reg])
 armtop("tbh",  [bs('111010001101'), rn_noarg, bs('11110000000'), bs('1'), bs_deref_reg_reg_lsl_1], [bs_deref_reg_reg_lsl_1])
 armtop("dsb",  [bs('111100111011'), bs('1111'), bs('1000'), bs('1111'), bs('0100'), barrier_option])
+
+armtop("adr", [bs('11110'), imm12_1, bs('100000'), bs('1111'), bs('0'), imm12_3, rd, imm12_8_t4], [rd, imm12_8_t4])
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 437303f3..b5ab60d0 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -1190,6 +1190,12 @@ def uxtab(ir, instr, a, b, c):
     return e, []
 
 
+def uxtah(ir, instr, a, b, c):
+    e = []
+    e.append(ExprAssign(a, b + (c & ExprInt(0xffff, 32))))
+    return e, []
+
+
 def bkpt(ir, instr, a):
     e = []
     e.append(ExprAssign(exception_flags, ExprInt(EXCEPT_SOFT_BP, 32)))
@@ -1294,6 +1300,13 @@ def rev(ir, instr, a, b):
     return e, []
 
 
+def rev16(ir, instr, a, b):
+    e = []
+    result = ExprCompose(b[8:16], b[:8], b[24:32], b[16:24])
+    e.append(ExprAssign(a, result))
+    return e, []
+
+
 def nop(ir, instr):
     e = []
     return e, []
@@ -1328,6 +1341,10 @@ def wfi(ir, instr):
     e = []
     return e, []
 
+def adr(ir, instr, arg1, arg2):
+    e = []
+    e.append(ExprAssign(arg1, (PC & ExprInt(0xfffffffc, 32)) + arg2))
+    return e, []
 
 COND_EQ = 0
 COND_NE = 1
@@ -1494,8 +1511,10 @@ mnemo_condm0 = {'add': add,
                 'ubfx': ubfx,
                 'bfc': bfc,
                 'rev': rev,
+                'rev16': rev16,
                 'clz': clz,
                 'uxtab': uxtab,
+                'uxtah': uxtah,
                 'bkpt': bkpt,
                 'smulbb': smul,
                 'smulbt': smul,
@@ -1579,6 +1598,7 @@ mnemo_nocond = {'lsr': lsr,
                 'cpsid': cpsid,
                 'wfe': wfe,
                 'wfi': wfi,
+                'adr': adr,
                 'orn': orn,
                 'smlabb': smlabb,
                 'smlabt': smlabt,
diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py
index 2110ccf7..c7d2961d 100644
--- a/test/arch/arm/arch.py
+++ b/test/arch/arm/arch.py
@@ -449,6 +449,13 @@ reg_tests_armt = [
 
     ("00000000    UXTB       R5, R0",
      "C5B2"),
+
+    ("00000000    UXTAB      R7, R0, R1",
+     "50FA81F7"),
+
+    ("00000000    UXTAH      R4, R0, R1",
+     "10FA81F4"),
+
     ("xxxxxxxx    BKPT       0x13",
      "13be"),
     ("xxxxxxxx    SVC        0x13",
@@ -493,6 +500,8 @@ reg_tests_armt = [
     ("xxxxxxxx    MOV        R1, R1 LSL 0x10",
      "4FEA0141"),
 
+    ("xxxxxxxx    MOV        R2, R11 LSR 0x1",
+     "4FEA5B02"),
 
     ("xxxxxxxx    ADD        R1, R4, 0x30",
      "04F13001"),
@@ -676,6 +685,9 @@ reg_tests_armt = [
     ("xxxxxxxx    DSB        SY",
      "bff34f8f"),
 
+    ("xxxxxxxx    CMP        R5, R0 LSR 0x8",
+     "B5EB102F"),
+
 
 ]
 print "#" * 40, 'armthumb', '#' * 40