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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-04-02 15:43:40 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-04-02 15:43:40 +0200 |
| commit | 0baf0ff24abd3e702eb14266302d4922e6caf731 (patch) | |
| tree | 19b5977e3bf0cf50d464ab1b8cb9a6fd9fd0bc36 | |
| parent | 2929d7256b90e92ef25fd298608d663b1616bebe (diff) | |
| download | box64-0baf0ff24abd3e702eb14266302d4922e6caf731.tar.gz box64-0baf0ff24abd3e702eb14266302d4922e6caf731.zip | |
[DYNAREC] Added 0F 73 opcode
| -rwxr-xr-x | src/dynarec/arm64_emitter.h | 10 | ||||
| -rwxr-xr-x | src/dynarec/dynarec_arm64_0f.c | 34 |
2 files changed, 44 insertions, 0 deletions
diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h index 3255abb3..ef849bf4 100755 --- a/src/dynarec/arm64_emitter.h +++ b/src/dynarec/arm64_emitter.h @@ -708,6 +708,12 @@ #define VSHL_16(Vd, Vn, shift) EMIT(SHL_vector(0, 0b0010 | (((shift)>>3)&1), (shift)&7, Vn, Vd)) #define VSHL_32(Vd, Vn, shift) EMIT(SHL_vector(0, 0b0100 | (((shift)>>3)&3), (shift)&7, Vn, Vd)) +#define SHL_scalar(U, size, Rm, R, S, Rn, Rd) (0b01<<30 | (U)<<29 | 0b11110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b010<<13 | (R)<<12 | (S)<<11 | 1<<10 | (Rn)<<5 | (Rd)) +#define SSHL_R_64(Vd, Vn, Vm) EMIT(SHL_scalar(0, 0b11, Vm, 0, 0, Vn, Vd)) + +#define SHL_scalar_imm(U, immh, immb, Rn, Rd) (0b01<<30 | 0b111110<<23 | (immh)<<19 | (immb)<<16 | 0b01010<<11 | 1<<10 | (Rn)<<5 | (Rd)) +#define SHL_64(Vd, Vn, shift) EMIT(SHL_scalar_imm(0, 0b1000 | (((shift)>>3)&7), (shift)&7, Vn, Vd)) + #define SHR_vector(Q, U, immh, immb, Rn, Rd) ((Q)<<30 | (U)<<29 | 0b011110<<23 | (immh)<<19 | (immb)<<16 | 0b00000<<11 | 1<<10 | (Rn)<<5 | (Rd)) #define VSHRQ_8(Vd, Vn, shift) EMIT(SHR_vector(1, 1, 0b0001, (8-(shift))&7, Vn, Vd)) #define VSHRQ_16(Vd, Vn, shift) EMIT(SHR_vector(1, 1, 0b0010 | (((16-(shift))>>3)&1), (16-(shift))&7, Vn, Vd)) @@ -724,6 +730,10 @@ #define VSSHR_16(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0010 | (((16-(shift))>>3)&1), (16-(shift))&7, Vn, Vd)) #define VSSHR_32(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0100 | (((32-(shift))>>3)&3), (32-(shift))&7, Vn, Vd)) +#define SHR_scalar_imm(U, immh, immb, o1, o0, Rn, Rd) (0b01<<30 | (U)<<29 | 0b111110<<23 | (immh)<<19 | (immb)<<16 | (o1)<<13 | (o0)<<12 | 1<<10 | (Rn)<<5 | (Rd)) +#define SSHR_64(Vd, Vn, shift) EMIT(SHR_scalar_imm(0, 0b1000 | (((64-(shift))>>3)&7), (64-(shift))&7, 0, 0, Vn, Vd)) +#define USHR_64(Vd, Vn, shift) EMIT(SHR_scalar_imm(1, 0b1000 | (((64-(shift))>>3)&7), (64-(shift))&7, 0, 0, Vn, Vd)) + #define EXT_vector(Q, Rm, imm4, Rn, Rd) ((Q)<<30 | 0b101110<<24 | (Rm)<<16 | (imm4)<<11 | (Rn)<<5 | (Rd)) #define VEXT_8(Rd, Rn, Rm, index) EMIT(EXT_vector(0, Rm, index, Rn, Rd)) #define VEXTQ_8(Rd, Rn, Rm, index) EMIT(EXT_vector(1, Rm, index, Rn, Rd)) diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c index 630d391b..f46dbc49 100755 --- a/src/dynarec/dynarec_arm64_0f.c +++ b/src/dynarec/dynarec_arm64_0f.c @@ -654,6 +654,40 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } break; + case 0x73: + nextop = F8; + switch((nextop>>3)&7) { + case 2: + INST_NAME("PSRLQ Em, Ib"); + GETEM(q0, 1); + u8 = F8; + if(u8) { + if (u8>63) { + VEOR(q0, q0, q0); + } else if(u8) { + USHR_64(q0, q0, u8); + } + PUTEM(q0); + } + break; + case 6: + INST_NAME("PSLLQ Em, Ib"); + GETEM(q0, 1); + u8 = F8; + if(u8) { + if (u8>63) { + VEOR(q0, q0, q0); + } else { + SHL_64(q0, q0, u8); + } + PUTEM(q0); + } + break; + default: + DEFAULT; + } + break; + case 0x77: INST_NAME("EMMS"); // empty MMX, FPU now usable |