[ARM+4_DYNAREC] Another fix for STMXCSR opcode when using SSE_FLUSHTO0

1 files changed, 1 insertions, 1 deletions

diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c
index 221b10a0..a8779464 100644
--- a/src/dynarec/arm64/dynarec_arm64_0f.c
+++ b/src/dynarec/arm64/dynarec_arm64_0f.c
@@ -1983,7 +1983,6 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         INST_NAME("STMXCSR Md");

                         addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);

                         LDRw_U12(x4, xEmu, offsetof(x64emu_t, mxcsr));

-                        STW(x4, ed, fixedaddress);

                         if(BOX64ENV(sse_flushto0)) {

                             // sync with fpsr, with mask from mxcsr

                             MRS_fpsr(x1);

@@ -1995,6 +1994,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                             //BFXILw(x3, x4, 7, 6); // this would the mask, but let's ignore that for now

                             BFIw(x4, x1, 0, 6); // inject back the flags

                         }

+                        STW(x4, ed, fixedaddress);

                         break;

                     case 4:

                         INST_NAME("XSAVE Ed");