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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-09-21 00:42:04 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-20 18:42:04 +0200 |
| commit | 15842f3464decd5d5c0809f394cf48af908fa454 (patch) | |
| tree | 72a80b1869351109feeab1732dc82e5224173c28 | |
| parent | e18846fac57c6b75fe9d918034159415e73c20cd (diff) | |
| download | box64-15842f3464decd5d5c0809f394cf48af908fa454.tar.gz box64-15842f3464decd5d5c0809f394cf48af908fa454.zip | |
[RV64_DYNAREC] Added more opcodes for vector (#1848)
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_660f_vector.c | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_660f_vector.c b/src/dynarec/rv64/dynarec_rv64_660f_vector.c index aad39907..dd453bca 100644 --- a/src/dynarec/rv64/dynarec_rv64_660f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_660f_vector.c @@ -932,9 +932,42 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i DEFAULT_VECTOR; } break; + case 0x72: + nextop = F8; + switch ((nextop >> 3) & 7) { + case 4: + INST_NAME("PSRAD Ex, Ib"); + SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1); + GETEX_vector(q0, 1, 1, VECTOR_SEW32); + u8 = F8; + if (u8 > 31) u8 = 31; + if (u8) { + VSRA_VI(q0, u8, q0, VECTOR_UNMASKED); + } + PUTEX_vector(q0, VECTOR_SEW32); + break; + default: + DEFAULT; + } + break; case 0x73: nextop = F8; switch ((nextop >> 3) & 7) { + case 2: + INST_NAME("PSRLQ Ex, Ib"); + SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1); + GETEX_vector(q0, 1, 1, VECTOR_SEW64); + u8 = F8; + if (u8) { + if (u8 > 63) { + VXOR_VV(q0, q0, q0, VECTOR_UNMASKED); + } else { + MOV64x(x4, u8); + VSRL_VX(q0, x4, q0, VECTOR_UNMASKED); + } + PUTEX_vector(q0, VECTOR_SEW64); + } + break; case 3: INST_NAME("PSRLDQ Ex, Ib"); SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1); @@ -1038,6 +1071,15 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i GETEX_vector(q1, 0, 0, VECTOR_SEW64); VADD_VV(q0, q0, q1, VECTOR_UNMASKED); break; + case 0xD5: + INST_NAME("PMULLW Gx, Ex"); + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW16, 1); + GETGX_vector(q0, 1, VECTOR_SEW16); + GETEX_vector(q1, 0, 0, VECTOR_SEW16); + v0 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL2); + VMUL_VV(q0, q0, q1, VECTOR_UNMASKED); + break; case 0xD6: INST_NAME("MOVQ Ex, Gx"); nextop = F8; @@ -1191,6 +1233,14 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i GETEX_vector(q1, 0, 0, VECTOR_SEW16); VMULHU_VV(q0, q1, q0, VECTOR_UNMASKED); break; + case 0xE9: + INST_NAME("PSUBSW Gx, Ex"); + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW16, 1); + GETGX_vector(q0, 1, VECTOR_SEW16); + GETEX_vector(q1, 0, 0, VECTOR_SEW16); + VSSUB_VV(q0, q1, q0, VECTOR_UNMASKED); + break; case 0xEB: INST_NAME("POR Gx, Ex"); nextop = F8; @@ -1199,6 +1249,14 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i GETEX_vector(q1, 0, 0, dyn->vector_eew); VOR_VV(q0, q0, q1, VECTOR_UNMASKED); break; + case 0xED: + INST_NAME("PADDSW Gx, Ex"); + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW16, 1); + GETGX_vector(q0, 1, VECTOR_SEW16); + GETEX_vector(q1, 0, 0, VECTOR_SEW16); + VSADD_VV(q0, q1, q0, VECTOR_UNMASKED); + break; case 0xEE: INST_NAME("PMAXSW Gx,Ex"); nextop = F8; |