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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-03-22 13:28:24 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-03-22 13:28:24 +0100 |
| commit | 1a12bd72697d9d304b6ee3c016660a863dba97bc (patch) | |
| tree | dcc2eea246971200a79397f8801aadabaec13ca7 | |
| parent | 04aa1af72e68a93d42afd90439744574f3668cda (diff) | |
| download | box64-1a12bd72697d9d304b6ee3c016660a863dba97bc.tar.gz box64-1a12bd72697d9d304b6ee3c016660a863dba97bc.zip | |
[DYNAREC] Added A8/A9 opcodes
| -rwxr-xr-x | src/dynarec/dynarec_arm64_00.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/dynarec/dynarec_arm64_00.c b/src/dynarec/dynarec_arm64_00.c index 5df9ab1b..c388e4f3 100755 --- a/src/dynarec/dynarec_arm64_00.c +++ b/src/dynarec/dynarec_arm64_00.c @@ -957,6 +957,22 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin SET_DFNONE(x1); break; + case 0xA8: + INST_NAME("TEST AL, Ib"); + SETFLAGS(X_ALL, SF_SET); + UXTBx(x1, xRAX); + u8 = F8; + MOV32w(x2, u8); + emit_test8(dyn, ninst, x1, x2, x3, x4, x5); + break; + case 0xA9: + INST_NAME("TEST EAX, Id"); + SETFLAGS(X_ALL, SF_SET); + i64 = F32S; + MOV64xw(x2, i64); + emit_test32(dyn, ninst, rex, xRAX, x2, x3, x4); + break; + case 0xB0: case 0xB1: case 0xB2: |