diff options
| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-08-09 19:31:58 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-09 13:31:58 +0200 |
| commit | 4407a1755106e56b7172c418e8cd8c0e4be6bf6e (patch) | |
| tree | 0ef623e96b334484dffd34ae5813f5d7fb9c7e01 | |
| parent | c7d6395aa65bece255ac8cfa19e04736baa85085 (diff) | |
| download | box64-4407a1755106e56b7172c418e8cd8c0e4be6bf6e.tar.gz box64-4407a1755106e56b7172c418e8cd8c0e4be6bf6e.zip | |
[RV64_DYNAREC] Fixed fpu_flags handling and enabled cosim in CI (#1722)
* [RV64_DYNAREC] Fixed fpu_flags handling * repeat until-pass
| -rw-r--r-- | .github/workflows/release.yml | 5 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_helper.c | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 768cecd7..0aa5e022 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -163,11 +163,16 @@ jobs: cd build if [[ ${{ matrix.platform }} == 'RISCV' ]]; then INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ ctest -j$(nproc) --output-on-failure + INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ BOX64_DYNAREC_TEST=2 ctest -j$(nproc) --repeat until-pass:20 --output-on-failure INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,v=false BOX64_DYNAREC=0 ctest -j$(nproc) --output-on-failure INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,v=false,zba=true,zbb=true,zbc=true,zbs=true ctest -j$(nproc) --output-on-failure + INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ BOX64_DYNAREC_TEST=2 QEMU_CPU=rv64,v=false,zba=true,zbb=true,zbc=true,zbs=true ctest -j$(nproc) --repeat until-pass:20 --output-on-failure INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,v=true,vlen=128,vext_spec=v1.0 ctest -j$(nproc) --output-on-failure + INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ BOX64_DYNAREC_TEST=2 QEMU_CPU=rv64,v=true,vlen=128,vext_spec=v1.0 ctest -j$(nproc) --repeat until-pass:20 --output-on-failure INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,v=true,vlen=256,vext_spec=v1.0 ctest -j$(nproc) --output-on-failure + INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ BOX64_DYNAREC_TEST=2 QEMU_CPU=rv64,v=true,vlen=256,vext_spec=v1.0 ctest -j$(nproc) --repeat until-pass:20 --output-on-failure INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,v=false,xtheadba=true,xtheadba=true,xtheadbb=true,xtheadbs=true,xtheadcondmov=true,xtheadmemidx=true,xtheadmempair=true,xtheadfmemidx=true,xtheadmac=true,xtheadfmv=true ctest -j$(nproc) --output-on-failure + INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ BOX64_DYNAREC_TEST=2 QEMU_CPU=rv64,v=false,xtheadba=true,xtheadba=true,xtheadbb=true,xtheadbs=true,xtheadcondmov=true,xtheadmemidx=true,xtheadmempair=true,xtheadfmemidx=true,xtheadmac=true,xtheadfmv=true ctest -j$(nproc) --repeat until-pass:20 --output-on-failure elif [[ ${{ matrix.platform }} == 'LARCH64' ]]; then INTERPRETER=qemu-loongarch64-static QEMU_LD_PREFIX=/usr/loongarch64-linux-gnu/ BOX64_DYNAREC_LA64NOEXT=1 ctest -j$(nproc) --repeat until-pass:20 --output-on-failure INTERPRETER=qemu-loongarch64-static QEMU_LD_PREFIX=/usr/loongarch64-linux-gnu/ BOX64_DYNAREC_TEST=2 BOX64_DYNAREC_LA64NOEXT=1 ctest -j$(nproc) --repeat until-pass:20 --output-on-failure diff --git a/src/dynarec/rv64/dynarec_rv64_helper.c b/src/dynarec/rv64/dynarec_rv64_helper.c index 3461cec0..3d96dbc2 100644 --- a/src/dynarec/rv64/dynarec_rv64_helper.c +++ b/src/dynarec/rv64/dynarec_rv64_helper.c @@ -1160,6 +1160,8 @@ static void x87_unreflectcache(dynarec_rv64_t* dyn, int ninst, int s1, int s2, i ADDI(s2, s2, a); ANDI(s2, s2, 7); SW(s2, xEmu, offsetof(x64emu_t, top)); + // update tags + LH(s1, xEmu, offsetof(x64emu_t, fpu_tags)); if(a>0) { SLLI(s3, xMASK, 16); // 0xffff0000 OR(s1, s1, s3); @@ -1167,6 +1169,7 @@ static void x87_unreflectcache(dynarec_rv64_t* dyn, int ninst, int s1, int s2, i } else { SLLI(s1, s1, -a*2); } + SH(s1, xEmu, offsetof(x64emu_t, fpu_tags)); } } |