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authorxctan <xctan@cirno.icu>2023-03-28 18:13:13 +0800
committerGitHub <noreply@github.com>2023-03-28 12:13:13 +0200
commit4a90199f63ea2e8ee16d11a20c5b9cc9abd11498 (patch)
treed09d1c0fd1d0afd169e3a93a5c3ad756240d6629
parent0dab0b596927c3a32a9d6f7937747e6602447627 (diff)
downloadbox64-4a90199f63ea2e8ee16d11a20c5b9cc9abd11498.tar.gz
box64-4a90199f63ea2e8ee16d11a20c5b9cc9abd11498.zip
[RV64_DYNAREC] Added more D8 opcodes (#646)
* [RV64_DYNAREC] Added D8 /{1,4} opcodes

* [RV64_DYNAREC] Added D8 /6 FDIV opcode
-rw-r--r--src/dynarec/rv64/dynarec_rv64_d8.c39
1 files changed, 39 insertions, 0 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_d8.c b/src/dynarec/rv64/dynarec_rv64_d8.c
index 6525245d..f7232a18 100644
--- a/src/dynarec/rv64/dynarec_rv64_d8.c
+++ b/src/dynarec/rv64/dynarec_rv64_d8.c
@@ -75,6 +75,45 @@ uintptr_t dynarec64_D8(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
                         FADDD(v1, v1, s0);
                     }
                     break;
+                case 1:
+                    INST_NAME("FMUL ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                    FLW(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FMULS(v1, v1, s0);
+                    } else {
+                        FCVTDS(s0, s0);
+                        FMULD(v1, v1, s0);
+                    }
+                    break;
+                case 4:
+                    INST_NAME("FSUB ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                    FLW(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FSUBS(v1, v1, s0);
+                    } else {
+                        FCVTDS(s0, s0);
+                        FSUBD(v1, v1, s0);
+                    }
+                    break;
+                case 6:
+                    INST_NAME("FDIV ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                    FLW(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FDIVS(v1, v1, s0);
+                    } else {
+                        FCVTDS(s0, s0);
+                        FDIVD(v1, v1, s0);
+                    }
+                    break;
                 default:
                     DEFAULT;
             }