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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2023-09-12 22:08:12 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-12 16:08:12 +0200 |
| commit | 50cf9c0e67936c1b5051ecab777cf8a5be1481a3 (patch) | |
| tree | c87883bf6b61c531ce3bc5056dcab586186628bd | |
| parent | 71ad38d742e5172048fbc83bb294bb4b44e7665a (diff) | |
| download | box64-50cf9c0e67936c1b5051ecab777cf8a5be1481a3.tar.gz box64-50cf9c0e67936c1b5051ecab777cf8a5be1481a3.zip | |
[CI] Test RISCV with bit-manipulation extensions on (#972)
* [CI] Test RISCV with bit-manipulation extensions on xthead extensions require qemu 8.1.0, therefore not available in CI * fix ADDSL
| -rw-r--r-- | .github/workflows/release.yml | 1 | ||||
| -rw-r--r-- | src/dynarec/rv64/rv64_emitter.h | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 9bfaf48a..966ea80f 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -110,6 +110,7 @@ jobs: if [[ ${{ matrix.platform }} != 'ANDROID' ]]; then if [[ ${{ matrix.platform }} == 'RISCV' ]]; then QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ ctest -j$(nproc) --rerun-failed --output-on-failure + QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,x-zba=true,x-zbb=true,x-zbc=true,x-zbs=true ctest -j$(nproc) --rerun-failed --output-on-failure elif [[ ${{ matrix.platform }} != 'X64' ]]; then QEMU_LD_PREFIX=/usr/aarch64-linux-gnu/ ctest -j$(nproc) --rerun-failed --output-on-failure else diff --git a/src/dynarec/rv64/rv64_emitter.h b/src/dynarec/rv64/rv64_emitter.h index 23f4f73d..4eebb353 100644 --- a/src/dynarec/rv64/rv64_emitter.h +++ b/src/dynarec/rv64/rv64_emitter.h @@ -311,7 +311,7 @@ f28–31 ft8–11 FP temporaries Caller #define ADDIz(rd, rs1, imm12) EMIT(I_type((imm12)&0b111111111111, rs1, 0b000, rd, rex.is32bits?0b0011011:0b0010011)) // rd = rs1 + (rs2 << imm2) -#define ADDSL(rd, rs1, rs2, imm2, scratch) if (!imm2) { \ +#define ADDSL(rd, rs1, rs2, imm2, scratch) if (!(imm2)) { \ ADD(rd, rs1, rs2); \ } else if (rv64_zba) { \ SHxADD(rd, rs2, imm2, rs1); \ |