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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-05-16 10:55:27 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-05-16 10:55:27 +0200 |
| commit | 5ea4b796a5fac103f9b5c88ea8e543e65600ab23 (patch) | |
| tree | 71cb9a0a0eed9a2dd74f519b7ea2c139320c8609 | |
| parent | 8fe7378f8613a7f249464bf5be48508bf02dc05c (diff) | |
| download | box64-5ea4b796a5fac103f9b5c88ea8e543e65600ab23.tar.gz box64-5ea4b796a5fac103f9b5c88ea8e543e65600ab23.zip | |
[DYNAREC] Fix ROL/ROR 8bits opcodes
| -rwxr-xr-x | src/dynarec/dynarec_arm64_00.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/dynarec/dynarec_arm64_00.c b/src/dynarec/dynarec_arm64_00.c index c8f4f4f1..ddd5ab2e 100755 --- a/src/dynarec/dynarec_arm64_00.c +++ b/src/dynarec/dynarec_arm64_00.c @@ -1309,7 +1309,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin switch((nextop>>3)&7) { case 0: INST_NAME("ROL Eb, Ib"); - SETFLAGS(X_OF|X_CF, SF_SUBSET); + SETFLAGS(X_OF|X_CF, SF_SET); GETEB(x1, 1); u8 = F8; MOV32w(x2, u8); @@ -1318,7 +1318,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin break; case 1: INST_NAME("ROR Eb, Ib"); - SETFLAGS(X_OF|X_CF, SF_SUBSET); + SETFLAGS(X_OF|X_CF, SF_SET); GETEB(x1, 1); u8 = F8; MOV32w(x2, u8); |