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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-12-19 04:47:06 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-18 21:47:06 +0100 |
| commit | 600ae18d4b8ff513e6e938ecfe7dfbc96a59d6ef (patch) | |
| tree | ef4c7a7a8eb86d736d0e9f2aca30f7786697e15f | |
| parent | 39aa02c19cc3df73d264bd668b2a600e4b922a16 (diff) | |
| download | box64-600ae18d4b8ff513e6e938ecfe7dfbc96a59d6ef.tar.gz box64-600ae18d4b8ff513e6e938ecfe7dfbc96a59d6ef.zip | |
[RV64_DYNAREC] Fixed 32bits SUBz (#2170)
| -rw-r--r-- | src/dynarec/rv64/rv64_emitter.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/dynarec/rv64/rv64_emitter.h b/src/dynarec/rv64/rv64_emitter.h index 7f360040..5c3279ea 100644 --- a/src/dynarec/rv64/rv64_emitter.h +++ b/src/dynarec/rv64/rv64_emitter.h @@ -124,7 +124,15 @@ // rd = rs1 - rs2 #define SUBxw(rd, rs1, rs2) EMIT(R_type(0b0100000, rs2, rs1, 0b000, rd, rex.w ? 0b0110011 : 0b0111011)) // rd = rs1 - rs2 -#define SUBz(rd, rs1, rs2) EMIT(R_type(0b0100000, rs2, rs1, 0b000, rd, rex.is32bits ? 0b0111011 : 0b0110011)) +#define SUBz(rd, rs1, rs2) \ + do { \ + if (!rex.is32bits) { \ + SUB(rd, rs1, rs2); \ + } else { \ + SUB(rd, rs1, rs2); \ + ZEROUP(rd); \ + } \ + } while (0) // rd = rs1<<rs2 #define SLL(rd, rs1, rs2) EMIT(R_type(0b0000000, rs2, rs1, 0b001, rd, 0b0110011)) // rd = (rs1<rs2)?1:0 |