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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2023-03-23 03:33:09 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-22 20:33:09 +0100 |
| commit | 72dc25abd1adfa199909370a9aaa16d6cc8c6bf3 (patch) | |
| tree | ee00c1f042c62d1a6e533dbae34055130e93ca3a | |
| parent | b85b3d9bbdca6a6842ba2b05f767b0e7f28d88ec (diff) | |
| download | box64-72dc25abd1adfa199909370a9aaa16d6cc8c6bf3.tar.gz box64-72dc25abd1adfa199909370a9aaa16d6cc8c6bf3.zip | |
[RV64_DYNAREC] Added more opcodes and some fixes (#619)
* [RV64_DYNAREC] Fixed SUB opcode * [RV64_DYNAREC] Added F6 /4 MUL opcode * [RV64_DYNAREC] Added 66 21 AND opcode
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_00.c | 14 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_66.c | 9 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_emit_math.c | 20 |
3 files changed, 31 insertions, 12 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_00.c b/src/dynarec/rv64/dynarec_rv64_00.c index 630666e7..98d5439f 100644 --- a/src/dynarec/rv64/dynarec_rv64_00.c +++ b/src/dynarec/rv64/dynarec_rv64_00.c @@ -1262,6 +1262,20 @@ uintptr_t dynarec64_00(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni MOV32w(x2, u8); emit_test8(dyn, ninst, x1, x2, x3, x4, x5); break; + case 4: + INST_NAME("MUL AL, Ed"); + SETFLAGS(X_ALL, SF_PENDING); + UFLAG_DF(x1, d_mul8); + GETEB(x1, 0); + ANDI(x2, xRAX, 0xff); + MULW(x1, x2, x1); + UFLAG_RES(x1); + LUI(x2, 0xffff0); + AND(xRAX, xRAX, x2); + SLLI(x1, x1, 48); + SRLI(x1, x1, 48); + OR(xRAX, xRAX, x1); + break; default: DEFAULT; } diff --git a/src/dynarec/rv64/dynarec_rv64_66.c b/src/dynarec/rv64/dynarec_rv64_66.c index cef86d4d..222cb60c 100644 --- a/src/dynarec/rv64/dynarec_rv64_66.c +++ b/src/dynarec/rv64/dynarec_rv64_66.c @@ -65,6 +65,15 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni case 0x0F: addr = dynarec64_660F(dyn, addr, ip, ninst, rex, ok, need_epilog); break; + case 0x21: + INST_NAME("AND Ew, Gw"); + SETFLAGS(X_ALL, SF_SET_PENDING); + nextop = F8; + GETGW(x2); + GETEW(x1, 0); + emit_and16(dyn, ninst, x1, x2, x4, x5); + EWBACK; + break; case 0x25: INST_NAME("AND AX, Iw"); SETFLAGS(X_ALL, SF_SET_PENDING); diff --git a/src/dynarec/rv64/dynarec_rv64_emit_math.c b/src/dynarec/rv64/dynarec_rv64_emit_math.c index 91cece12..7d8ed89a 100644 --- a/src/dynarec/rv64/dynarec_rv64_emit_math.c +++ b/src/dynarec/rv64/dynarec_rv64_emit_math.c @@ -321,10 +321,7 @@ void emit_sub8c(dynarec_rv64_t* dyn, int ninst, int s1, int c, int s2, int s3, i { CLEAR_FLAGS(); - IFX(X_ALL|X_PEND) { - MOV32w(s5, c&0xff); - } - + MOV32w(s5, c&0xff); IFX(X_PEND) { SB(s1, xEmu, offsetof(x64emu_t, op1)); SB(s5, xEmu, offsetof(x64emu_t, op2)); @@ -335,20 +332,19 @@ void emit_sub8c(dynarec_rv64_t* dyn, int ninst, int s1, int c, int s2, int s3, i IFX(X_AF | X_CF | X_OF) { // for later flag calculation - NOT(s5, s1); + NOT(s2, s1); } - SUBW(s1, s1, s3); - ANDI(s1, s1, 0xff); - - IFX(X_PEND) { - SB(s1, xEmu, offsetof(x64emu_t, res)); - } + SUB(s1, s1, s5); IFX(X_SF) { BGE(s1, xZR, 8); ORI(xFlags, xFlags, 1 << F_SF); } - CALC_SUB_FLAGS(s5, s2, s1, s3, s4, 8); + ANDI(s1, s1, 0xff); + IFX(X_PEND) { + SB(s1, xEmu, offsetof(x64emu_t, res)); + } + CALC_SUB_FLAGS(s2, s5, s1, s3, s4, 8); IFX(X_ZF) { BNEZ(s1, 8); ORI(xFlags, xFlags, 1 << F_ZF); |