[RV64_DYNAREC] Preparing float/double handling

2 files changed, 25 insertions, 28 deletions

diff --git a/src/dynarec/rv64/rv64_epilog.S b/src/dynarec/rv64/rv64_epilog.S
index 9b97c232..6a299d9d 100644
--- a/src/dynarec/rv64/rv64_epilog.S
+++ b/src/dynarec/rv64/rv64_epilog.S
@@ -7,6 +7,8 @@
 .align 4
 
 .global rv64_epilog
+.global rv64_epilog_fast
+
 rv64_epilog:
     //update register -> emu
     sd      x16, (a0)
@@ -33,27 +35,7 @@ rv64_epilog:
     or      x8, x8, x5
     sd      x8, 128(a0)     //xFlags
     sd      x7, 136(a0)     // put back reg value in emu, including EIP (so x7 must be EIP now)
-    //restore all used register
-    ld      ra, (sp)  // save ra
-    ld      x8, 8(sp) // save fp
-    ld      x18, 16(sp)
-    ld      x19, 24(sp)
-    ld      x20, 32(sp)
-    ld      x21, 40(sp)
-    ld      x22, 48(sp)
-    ld      x23, 56(sp)
-    ld      x24, 64(sp)
-    ld      x25, 72(sp)
-    ld      x26, 80(sp)
-    ld      x27, 88(sp)
-    fsd     f8, 96(sp)
-    fsd     f9, 104(sp)
-    addi    sp,  sp, (8 * 14)
-    //end, return...
-    ret
-
-
-.global rv64_epilog_fast
+    // fallback to epilog_fast now, just restoring saved regs
 rv64_epilog_fast:
     ld      ra, (sp)  // save ra
     ld      x8, 8(sp) // save fp
@@ -67,8 +49,16 @@ rv64_epilog_fast:
     ld      x25, 72(sp)
     ld      x26, 80(sp)
     ld      x27, 88(sp)
-    fsd     f8, 96(sp)
-    fsd     f9, 104(sp)
-    addi    sp,  sp, (8 * 14)
+    fld     f18, (12*8)(sp)
+    fld     f19, (13*8)(sp)
+    fld     f20, (14*8)(sp)
+    fld     f21, (15*8)(sp)
+    fld     f22, (16*8)(sp)
+    fld     f23, (17*8)(sp)
+    fld     f24, (18*8)(sp)
+    fld     f25, (19*8)(sp)
+    fld     f26, (20*8)(sp)
+    fld     f27, (21*8)(sp)
+    addi    sp,  sp, (8 * 22)
     //end, return...
     ret
diff --git a/src/dynarec/rv64/rv64_prolog.S b/src/dynarec/rv64/rv64_prolog.S
index 06d275b7..0817bdc1 100644
--- a/src/dynarec/rv64/rv64_prolog.S
+++ b/src/dynarec/rv64/rv64_prolog.S
@@ -11,7 +11,7 @@
 .global rv64_prolog
 rv64_prolog:
     //save all 18 used register
-    addi    sp,  sp, -(8 * 14)
+    addi    sp,  sp, -(8 * 22)
     sd      ra, (sp)  // save ra
     sd      x8, 8(sp) // save fp
     sd      x18, 16(sp)
@@ -24,9 +24,16 @@ rv64_prolog:
     sd      x25, 72(sp)
     sd      x26, 80(sp)
     sd      x27, 88(sp)
-    fsd     f8, 96(sp)
-    fsd     f9, 104(sp)
-    // save f18-f27 too probably
+    fsd     f18, (12*8)(sp)
+    fsd     f19, (13*8)(sp)
+    fsd     f20, (14*8)(sp)
+    fsd     f21, (15*8)(sp)
+    fsd     f22, (16*8)(sp)
+    fsd     f23, (17*8)(sp)
+    fsd     f24, (18*8)(sp)
+    fsd     f25, (19*8)(sp)
+    fsd     f26, (20*8)(sp)
+    fsd     f27, (21*8)(sp)
     //setup emu -> register
     ld      x16, (a0)
     ld      x17, 8(a0)