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| author | phorcys <phorcys@126.com> | 2025-07-11 14:06:37 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-11 08:06:37 +0200 |
| commit | 78460724ea0770f4c5b85ec117273d4a3d54b230 (patch) | |
| tree | 3c374c49f202b75b71d986274a3bee563801dff0 | |
| parent | 6ea020eb54168bdf14155670baa0bb4b0abd4a3f (diff) | |
| download | box64-78460724ea0770f4c5b85ec117273d4a3d54b230.tar.gz box64-78460724ea0770f4c5b85ec117273d4a3d54b230.zip | |
[LA64_DYNAREC] Add la64 avx shift ops with imm operand. (#2805)
VEX.128/256 66.0F shift imm ops: * 71 VPSRLW/VPSRAW/VPSLLW * 72 VPSRLD/VPSRAD/VPSLLD * 73 VPSRLQ/VPSLLQ/VPSRLDQ/VPSLLDQ
| -rw-r--r-- | src/dynarec/la64/dynarec_la64_avx_66_0f.c | 130 | ||||
| -rw-r--r-- | src/dynarec/la64/la64_emitter.h | 45 |
2 files changed, 175 insertions, 0 deletions
diff --git a/src/dynarec/la64/dynarec_la64_avx_66_0f.c b/src/dynarec/la64/dynarec_la64_avx_66_0f.c index 4fff9660..0c707a28 100644 --- a/src/dynarec/la64/dynarec_la64_avx_66_0f.c +++ b/src/dynarec/la64/dynarec_la64_avx_66_0f.c @@ -285,6 +285,136 @@ uintptr_t dynarec64_AVX_66_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, } } break; + case 0x71: + nextop = F8; + switch ((nextop >> 3) & 7) { + case 2: + INST_NAME("VPSRLW Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 15) { + VXOR_Vxy(v0, v0, v0); + } else { + VSRLIxy(H, v0, v1, u8); + } + break; + case 4: + INST_NAME("VPSRAW Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 15) u8 = 15; + if (u8) { + VSRAIxy(H, v0, v1, u8); + } + break; + case 6: + INST_NAME("VPSLLW Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 15) { + VXOR_Vxy(v0, v0, v0); + } else { + VSLLIxy(H, v0, v1, u8); + } + break; + default: + *ok = 0; + DEFAULT; + } + break; + case 0x72: + nextop = F8; + switch ((nextop >> 3) & 7) { + case 2: + INST_NAME("VPSRLD Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 31) { + VXOR_Vxy(v0, v0, v0); + } else { + VSRLIxy(W, v0, v1, u8); + } + break; + case 4: + INST_NAME("VPSRAD Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 31) u8 = 31; + if (u8) { + VSRAIxy(W, v0, v1, u8); + } + break; + case 6: + INST_NAME("VPSLLD Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 31) { + VXOR_Vxy(v0, v0, v0); + } else { + VSLLIxy(W, v0, v1, u8); + } + break; + default: + DEFAULT; + } + break; + case 0x73: + nextop = F8; + switch ((nextop >> 3) & 7) { + case 2: + INST_NAME("VPSRLQ Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 63) { + VXOR_Vxy(v0, v0, v0); + } else { + VSRLIxy(D, v0, v1, u8); + } + break; + case 3: + INST_NAME("VPSRLDQ Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 15) { + VXOR_Vxy(v0, v0, v0); + } else { + VBSRL_Vxy(v0, v1, u8); + } + break; + case 6: + INST_NAME("VPSLLQ Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 63) { + VXOR_Vxy(v0, v0, v0); + } else { + VSLLIxy(D, v0, v1, u8); + } + break; + case 7: + INST_NAME("VPSLLDQ Vx, Ex, Ib"); + GETEYxy(v1, 0, 1); + GETVYxy_empty(v0); + u8 = F8; + if (u8 > 15) { + VXOR_Vxy(v0, v0, v0); + } else { + VBSLL_Vxy(v0, v1, u8); + } + break; + default: + DEFAULT; + } + break; case 0x7E: INST_NAME("VMOVD Ed, Gx"); nextop = F8; diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h index 00ca7bdd..0472481b 100644 --- a/src/dynarec/la64/la64_emitter.h +++ b/src/dynarec/la64/la64_emitter.h @@ -2657,4 +2657,49 @@ LSX instruction starts with V, LASX instruction starts with XV. VXOR_V(vd, vj, vk); \ } \ } while (0) + +#define VBSLL_Vxy(vd, vj, imm) \ + do { \ + if (vex.l) { \ + XVBSLL_V(vd, vj, imm); \ + } else { \ + VBSLL_V(vd, vj, imm); \ + } \ + } while (0) + +#define VBSRL_Vxy(vd, vj, imm) \ + do { \ + if (vex.l) { \ + XVBSRL_V(vd, vj, imm); \ + } else { \ + VBSRL_V(vd, vj, imm); \ + } \ + } while (0) + +#define VSLLIxy(width, vd, vj, imm) \ + do { \ + if (vex.l) { \ + XVSLLI_##width(vd, vj, imm); \ + } else { \ + VSLLI_##width(vd, vj, imm); \ + } \ + } while (0) + +#define VSRLIxy(width, vd, vj, imm) \ + do { \ + if (vex.l) { \ + XVSRLI_##width(vd, vj, imm); \ + } else { \ + VSRLI_##width(vd, vj, imm); \ + } \ + } while (0) + +#define VSRAIxy(width, vd, vj, imm) \ + do { \ + if (vex.l) { \ + XVSRAI_##width(vd, vj, imm); \ + } else { \ + VSRAI_##width(vd, vj, imm); \ + } \ + } while (0) #endif //__ARM64_EMITTER_H__ |