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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-12-19 03:54:08 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-18 20:54:08 +0100 |
| commit | 7dcb86f500c461a345d6d413b8eb543f3ee733dc (patch) | |
| tree | dce704a2d10a9a545cc40602f8c5c31a9c2007b1 | |
| parent | f873255a19704f9be0be110f2b7e5d219d2ea0a6 (diff) | |
| download | box64-7dcb86f500c461a345d6d413b8eb543f3ee733dc.tar.gz box64-7dcb86f500c461a345d6d413b8eb543f3ee733dc.zip | |
[RV64_DYNAREC] Fixed 32bit ADDIz (#2168)
| -rw-r--r-- | src/dynarec/rv64/rv64_emitter.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/dynarec/rv64/rv64_emitter.h b/src/dynarec/rv64/rv64_emitter.h index 4e699fa7..7f360040 100644 --- a/src/dynarec/rv64/rv64_emitter.h +++ b/src/dynarec/rv64/rv64_emitter.h @@ -424,7 +424,15 @@ // rd = rs1 + imm12 #define ADDIxw(rd, rs1, imm12) EMIT(I_type((imm12) & 0b111111111111, rs1, 0b000, rd, rex.w ? 0b0010011 : 0b0011011)) // rd = rs1 + imm12 -#define ADDIz(rd, rs1, imm12) EMIT(I_type((imm12) & 0b111111111111, rs1, 0b000, rd, rex.is32bits ? 0b0011011 : 0b0010011)) +#define ADDIz(rd, rs1, imm12) \ + do { \ + if (!rex.is32bits) { \ + ADDI(rd, rs1, imm12); \ + } else { \ + ADDIW(rd, rs1, imm12); \ + ZEROUP(rd); \ + } \ + } while (0) // rd = rs1 + (rs2 << imm2) #define ADDSL(rd, rs1, rs2, imm2, scratch) \ |