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authorptitSeb <sebastien.chev@gmail.com>2023-05-13 15:27:32 +0000
committerptitSeb <sebastien.chev@gmail.com>2023-05-13 15:27:32 +0000
commit9de2aa55cdafac5a8f0aa38345d829f086a04cf6 (patch)
tree5170229c4da6d7b371c0edae7078cb51bbf0da8d
parent6ac2376aacf1f7c69a50169dba4fefca9f62f8c5 (diff)
downloadbox64-9de2aa55cdafac5a8f0aa38345d829f086a04cf6.tar.gz
box64-9de2aa55cdafac5a8f0aa38345d829f086a04cf6.zip
[RV64_DYNAREC] Small optim for GETSEW(...) helper macro
-rw-r--r--src/dynarec/rv64/dynarec_rv64_helper.h3
-rw-r--r--src/dynarec/rv64/rv64_emitter.h4
2 files changed, 4 insertions, 3 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_helper.h b/src/dynarec/rv64/dynarec_rv64_helper.h
index d76bd552..66e228b6 100644
--- a/src/dynarec/rv64/dynarec_rv64_helper.h
+++ b/src/dynarec/rv64/dynarec_rv64_helper.h
@@ -150,8 +150,7 @@
 //GETSEW will use i for ed, and can use r3 for wback. This is the Signed version
 #define GETSEW(i, D) if(MODREG) {           \
                     wback = xRAX+(nextop&7)+(rex.b<<3);\
-                    SLLI(i, wback, 48);     \
-                    SRAI(i, i, 48);         \
+                    if(rv64_zbb) SEXTH(i, wback); else {SLLI(i, wback, 48); SRAI(i, i, 48);}\
                     ed = i;                 \
                     wb1 = 0;                \
                 } else {                    \
diff --git a/src/dynarec/rv64/rv64_emitter.h b/src/dynarec/rv64/rv64_emitter.h
index 3ee6bd11..bc737cc0 100644
--- a/src/dynarec/rv64/rv64_emitter.h
+++ b/src/dynarec/rv64/rv64_emitter.h
@@ -572,7 +572,9 @@ f28–31  ft8–11  FP temporaries                  Caller
 // Sign-extend half-word
 #define SEXTH(rd, rs)           EMIT(R_type(0b0110000, 0b00101, rs, 0b001, rd, 0b0010011))
 // Zero-extend half-word
-#define ZEXTH(rd, rs)           if(rv64_zbb) EMIT(R_type(0b0000100, 0b00000, rs, 0b100, rd, 0b0111011)); else {SLLI(rd, rs, 48); SRLI(rd, rd, 48);}
+#define ZEXTH_(rd, rs)          EMIT(R_type(0b0000100, 0b00000, rs, 0b100, rd, 0b0111011))
+// Zero-extend half-word
+#define ZEXTH(rd, rs)           if(rv64_zbb) ZEXTH_(rd, rs); else {SLLI(rd, rs, 48); SRLI(rd, rd, 48);}
 // Rotate left (register)
 #define ROL(rd, rs1, rs2)       EMIT(R_type(0b0110000, rs2, rs1, 0b001, rd, 0b0110011))
 // Rotate left word (register)