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| author | ptitSeb <sebastien.chev@gmail.com> | 2023-03-13 12:12:45 +0000 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2023-03-13 12:12:45 +0000 |
| commit | a6d32f4a62556599a6a42462fefb15c8a2726e86 (patch) | |
| tree | a94200659389d7b1bf5a48eb18b7154e10433847 | |
| parent | a5f9bda13150e5548d0e3524bc6245c2e8ad5c54 (diff) | |
| download | box64-a6d32f4a62556599a6a42462fefb15c8a2726e86.tar.gz box64-a6d32f4a62556599a6a42462fefb15c8a2726e86.zip | |
[RV64_DYNAREC] Fixed rv64_epilog_fast, but it's not used for now
| -rw-r--r-- | src/dynarec/rv64/rv64_epilog.S | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/src/dynarec/rv64/rv64_epilog.S b/src/dynarec/rv64/rv64_epilog.S index 610a2483..af04279b 100644 --- a/src/dynarec/rv64/rv64_epilog.S +++ b/src/dynarec/rv64/rv64_epilog.S @@ -49,13 +49,20 @@ rv64_epilog: .global rv64_epilog_fast rv64_epilog_fast: - //restore all used register ld ra, (sp) // save ra ld x8, 8(sp) // save fp - ld x16, 16(sp) - ld x17, 24(sp) - fld f8, 32(sp) - fld f9, 40(sp) - addi sp, sp, (8 * (2+4)) + ld x18, 16(sp) + ld x19, 24(sp) + ld x20, 32(sp) + ld x21, 40(sp) + ld x22, 48(sp) + ld x23, 56(sp) + ld x24, 64(sp) + ld x25, 72(sp) + ld x26, 80(sp) + ld x27, 88(sp) + fsd f8, 96(sp) + fsd f9, 104(sp) + addi sp, sp, (8 * 14) //end, return... ret |