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authorptitSeb <sebastien.chev@gmail.com>2021-04-03 10:37:00 +0200
committerptitSeb <sebastien.chev@gmail.com>2021-04-03 10:37:00 +0200
commitb239bec2c5d63120e4aa761b6b014af6e50d0633 (patch)
tree8cc7e1e918a5ce1c57c58befa9e35d2707ff6f07
parentd0f05fed3b59201390a184a9fa79b0e8bd7b9c0c (diff)
downloadbox64-b239bec2c5d63120e4aa761b6b014af6e50d0633.tar.gz
box64-b239bec2c5d63120e4aa761b6b014af6e50d0633.zip
[DYNAREC] Better 0F 77 EMMS emulation
-rwxr-xr-xsrc/dynarec/dynarec_arm64_0f.c2
-rwxr-xr-xsrc/dynarec/dynarec_arm64_helper.c2
-rwxr-xr-xsrc/dynarec/dynarec_arm64_helper.h3
3 files changed, 5 insertions, 2 deletions
diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c
index 653be8ca..5d465fb7 100755
--- a/src/dynarec/dynarec_arm64_0f.c
+++ b/src/dynarec/dynarec_arm64_0f.c
@@ -691,7 +691,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0x77:

             INST_NAME("EMMS");

             // empty MMX, FPU now usable

-            // mmx_purge_cache?

+            mmx_purgecache(dyn, ninst, x1);

             /*emu->top = 0;

             emu->fpu_stack = 0;*/ //TODO: Check if something is needed here?

             break;

diff --git a/src/dynarec/dynarec_arm64_helper.c b/src/dynarec/dynarec_arm64_helper.c
index 20512247..b5193bb1 100755
--- a/src/dynarec/dynarec_arm64_helper.c
+++ b/src/dynarec/dynarec_arm64_helper.c
@@ -911,7 +911,7 @@ int mmx_get_reg_empty(dynarec_arm_t* dyn, int ninst, int s1, int a)
 #endif
 }
 // purge the MMX cache only(needs 3 scratch registers)
-static void mmx_purgecache(dynarec_arm_t* dyn, int ninst, int s1)
+void mmx_purgecache(dynarec_arm_t* dyn, int ninst, int s1)
 {
 #if STEP > 1
     int old = -1;
diff --git a/src/dynarec/dynarec_arm64_helper.h b/src/dynarec/dynarec_arm64_helper.h
index b356e0d4..651ab7ef 100755
--- a/src/dynarec/dynarec_arm64_helper.h
+++ b/src/dynarec/dynarec_arm64_helper.h
@@ -678,6 +678,7 @@ void* arm64_next(x64emu_t* emu, uintptr_t addr);
 #define fpu_popcache    STEPNAME(fpu_popcache)
 #define fpu_reset       STEPNAME(fpu_reset)
 #define fpu_purgecache  STEPNAME(fpu_purgecache)
+#define mmx_purgecache  STEPNAME(mmx_purgecache)
 #ifdef HAVE_TRACE
 #define fpu_reflectcache STEPNAME(fpu_reflectcache)
 #endif
@@ -817,6 +818,8 @@ void sse_purge07cache(dynarec_arm_t* dyn, int ninst, int s1);
 void fpu_reset(dynarec_arm_t* dyn, int ninst);
 // purge the FPU cache (needs 3 scratch registers)
 void fpu_purgecache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3);
+// purge MMX cache
+void mmx_purgecache(dynarec_arm_t* dyn, int ninst, int s1);
 #ifdef HAVE_TRACE
 void fpu_reflectcache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3);
 #endif