[DYNAREC] Fixed a few opcodes: BTR/BTC/BTS 16bits, CVTTPD2DQ and PSHUF(L/H)W

3 files changed, 12 insertions, 23 deletions

diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c
index 76512132..b3bd2322 100755
--- a/src/dynarec/dynarec_arm64_660f.c
+++ b/src/dynarec/dynarec_arm64_660f.c
@@ -910,7 +910,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             B_NEXT(cNE);

             MOV32w(x1, 1);

             LSLxw_REG(x1, x1, x2);

-            EORxw_REG(ed, ed, x1);

+            EORx_REG(ed, ed, x1);

             if(wback) {

                 STRH_U12(ed, wback, fixedaddress);

             }

@@ -971,7 +971,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             B_NEXT(cEQ);

             MOV32w(x1, 1);

             LSLxw_REG(x1, x1, x2);

-            EORxw_REG(ed, ed, x1);

+            EORx_REG(ed, ed, x1);

             if(wback) {

                 STRH_U12(ed, wback, fixedaddress);

             }

@@ -1021,7 +1021,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             ANDw_mask(x1, x1, 0, 0);  //mask=1

             MOV32w(x1, 1);

             LSLxw_REG(x1, x1, x2);

-            EORxw_REG(ed, ed, x1);

+            EORx_REG(ed, ed, x1);

             if(wback) {

                 STRH_U12(ed, wback, fixedaddress);

             }

@@ -1289,29 +1289,12 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             SQSHRN2_16(v0, q1, 16);

             break;

         case 0xE6:

-            INST_NAME("CVTPD2DQ Gx, Ex");

+            INST_NAME("CVTTPD2DQ Gx, Ex");

             nextop = F8;

             GETEX(v1, 0);

             GETGX_empty(v0);

-            #ifdef PRECISE_CVT

-            LDRH_U12(x1, xEmu, offsetof(x64emu_t, mxcsr));

-            UBFXx(x1, x1, 13, 2);   // extract round requested

-            LSLx_REG(x1, x1, 3);

-            ADDx_U12(x1, x1, 8);    // add the actual add+jump opcodes

-            // Construct a "switch case", with each case 2 instructions, so 8 bytes

-            BL(+4); // Branch with Link to next, so LR gets next PC address

-            ADDx_REG(xLR, xLR, x1);

-            B(xLR); // could use RET, but it's not really one

-            VFCVTNSQD(v0, v1);  // 0: Nearest (even)

-            B_NEXT_nocond;

-            VFCVTMSQD(v0, v1);  // 1: Toward -inf

-            B_NEXT_nocond;

-            VFCVTPSQD(v0, v1);  // 2: Toward +inf

-            B_NEXT_nocond;

-            VFCVTZSQD(v0, v1);  // 3: Toward 0

-            #else

-            VFCVTNSQD(v0, v1);

-            #endif

+            VFCVTNSQD(v0, v1);  // convert double -> int64

+            SQXTN_32(v0, v0);   // convert int64 -> int32 with saturation in lower part, RaZ high part

             break;

         case 0xE7:

             INST_NAME("MOVNTDQ Ex, Gx");

diff --git a/src/dynarec/dynarec_arm64_f20f.c b/src/dynarec/dynarec_arm64_f20f.c
index e9a53d0f..e2b01575 100755
--- a/src/dynarec/dynarec_arm64_f20f.c
+++ b/src/dynarec/dynarec_arm64_f20f.c
@@ -257,6 +257,9 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             VMOVQDfrom(d0, 0, x2);

             VTBL1_8(d0, v1, d0);

             VMOVeD(v0, 0, d0, 0);

+            if(v0!=v1) {

+                VMOVeD(v0, 1, v1, 1);

+            }

             break;

 

         case 0x7C:

diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c
index 741fb660..f398f23c 100755
--- a/src/dynarec/dynarec_arm64_f30f.c
+++ b/src/dynarec/dynarec_arm64_f30f.c
@@ -303,6 +303,9 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             VMOVQDfrom(d0, 0, x2);

             VTBL1_8(d0, v1, d0);

             VMOVeD(v0, 1, d0, 0);

+            if(v0!=v1) {

+                VMOVeD(v0, 0, v1, 0);

+            }

             break;

 

         case 0x7E: