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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-03-21 20:37:25 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-03-21 20:37:25 +0100 |
| commit | c8b6834a5e4593c33554fa051658feaf9292f53e (patch) | |
| tree | 32c282527c84f63196ecce62392041c271ccb10b | |
| parent | e15eb5a7f6e421deba49b9ab0d28b84231c68033 (diff) | |
| download | box64-c8b6834a5e4593c33554fa051658feaf9292f53e.tar.gz box64-c8b6834a5e4593c33554fa051658feaf9292f53e.zip | |
[DYNAREC] Added F3 0F 7E/7F opcodes
| -rwxr-xr-x | src/dynarec/arm64_emitter.h | 4 | ||||
| -rwxr-xr-x | src/dynarec/dynarec_arm64_f30f.c | 32 |
2 files changed, 34 insertions, 2 deletions
diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h index 04aed180..a2ad2561 100755 --- a/src/dynarec/arm64_emitter.h +++ b/src/dynarec/arm64_emitter.h @@ -577,8 +577,8 @@ #define FMOVxD1(Xd, Vn) EMIT(FMOV_general(1, 0b10, 0b01, ob110, Vn, Xd)) #define FMOV_register(type, Rn, Rd) (0b11110<<24 | (type)<<22 | 1<<21 | (Rn)<<5 | (Rd)) -#define FMOVS(Sd, Sn) EMIT(FMOV_register, 0b00, Sn, Sd) -#define FMOVD(Dd, Dn) EMIT(FMOV_register, 0b01, Dn, Dd) +#define FMOVS(Sd, Sn) EMIT(FMOV_register(0b00, Sn, Sd)) +#define FMOVD(Dd, Dn) EMIT(FMOV_register(0b01, Dn, Dd)) // VMOV #define VMOV_element(imm5, imm4, Rn, Rd) (1<<30 | 1<<29 | 0b01110000<<21 | (imm5)<<16 | (imm4)<<11 | 1<<10 | (Rn)<<5 | (Rd)) diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c index 9072de5c..21b3531e 100755 --- a/src/dynarec/dynarec_arm64_f30f.c +++ b/src/dynarec/dynarec_arm64_f30f.c @@ -161,6 +161,38 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n VMOVeS(v0, 0, d1, 0); break; + case 0x7E: + INST_NAME("MOVQ Gx, Ex"); + nextop = F8; + GETG; + if(MODREG) { + v1 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3)); + v0 = sse_get_reg_empty(dyn, ninst, x1, gd); + FMOVD(v0, v1); + } else { + v0 = sse_get_reg_empty(dyn, ninst, x1, gd); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0); + VLDR64_U12(v0, ed, fixedaddress); + } + break; + case 0x7F: + INST_NAME("MOVDQU Ex,Gx"); + nextop = F8; + GETG; + if(MODREG) { + v0 = sse_get_reg(dyn, ninst, x1, gd); + v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3)); + VMOVQ(v1, v0); + } else { + v0 = sse_get_reg(dyn, ninst, x1, gd); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xff0<<3, 7, rex, 0, 0); + VMOVQDto(x2, v0, 0); + STRx_U12(x2, ed, fixedaddress+0); + VMOVQDto(x2, v0, 1); + STRx_U12(x2, ed, fixedaddress+8); + } + break; + default: DEFAULT; } |