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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-03-31 16:58:29 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-03-31 16:58:29 +0200 |
| commit | cbf4e37bbab3a4b6595d66037163fee316a01995 (patch) | |
| tree | 2d4a7e592ab0b4fd92ed9590074ef6ea4e1416a7 | |
| parent | 74b70253b25328f171f11bd2776dadb553cefc84 (diff) | |
| download | box64-cbf4e37bbab3a4b6595d66037163fee316a01995.tar.gz box64-cbf4e37bbab3a4b6595d66037163fee316a01995.zip | |
[DYNAREC] Added 0F 38 04 opcode
| -rwxr-xr-x | src/dynarec/dynarec_arm64_0f.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c index c528e99e..41ecf035 100755 --- a/src/dynarec/dynarec_arm64_0f.c +++ b/src/dynarec/dynarec_arm64_0f.c @@ -281,6 +281,30 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin FCOMI(x1, x2); break; + case 0x38: + //SSE3 + nextop=F8; + switch(nextop) { + + case 0x04: + INST_NAME("PMADDUBSW Gm,Em"); + nextop = F8; + GETGM(q0); + GETEM(q1, 0); + v0 = fpu_get_scratch(dyn); + v1 = fpu_get_scratch(dyn); + UXTL_8(v0, q0); // this is unsigned, so 0 extended + SXTL_8(v1, q1); // this is signed + VMULQ_16(v0, v0, v1); + SADDLPQ_16(v1, v0); + SQXTN_16(q0, v1); + break; + + default: + DEFAULT; + } + break; + #define GO(GETFLAGS, NO, YES, F) \ READFLAGS(F); \ GETFLAGS; \ |