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authorptitSeb <sebastien.chev@gmail.com>2022-04-13 07:43:48 +0200
committerptitSeb <sebastien.chev@gmail.com>2022-04-13 07:43:48 +0200
commitdc9144f8f4b15f74c987e0fb0970a501001a03d0 (patch)
tree4b1889ebced6344c14f30ab2ff455db8fe6b88a0
parent5538ffde53c5300918b6847e4c3243e3a3212cbd (diff)
downloadbox64-dc9144f8f4b15f74c987e0fb0970a501001a03d0.tar.gz
box64-dc9144f8f4b15f74c987e0fb0970a501001a03d0.zip
Fixed Page16K selection for M1 and LoongArch build
-rwxr-xr-xCMakeLists.txt7
1 files changed, 6 insertions, 1 deletions
diff --git a/CMakeLists.txt b/CMakeLists.txt
index b5e857b3..d1b498fe 100755
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -30,19 +30,24 @@ if(RV64)
     set(LD80BITS OFF CACHE BOOL "")
     set(NOALIGN OFF CACHE BOOL "")
     set(ARM_DYNAREC OFF CACHE BOOL "")  
+    set(PAGE16K OFF CACHE BOOL "")
 endif()
 if(PPC64LE)
     set(LD80BITS OFF CACHE BOOL "")
     set(NOALIGN OFF CACHE BOOL "")
     set(ARM_DYNAREC OFF CACHE BOOL "")
+    set(PAGE16K OFF CACHE BOOL "")
 endif()
 if(RK3399 OR ODROIDN2 OR RPI4ARM64 OR RK3326 OR TEGRAX1 OR PHYTIUM OR SD845 OR LX2160A OR M1)
     set(LD80BITS OFF CACHE BOOL "")
     set(NOALIGN OFF CACHE BOOL "")
     set(ARM_DYNAREC ON CACHE BOOL "")
 endif()
+if(RK3399 OR ODROIDN2 OR RPI4ARM64 OR RK3326 OR TEGRAX1 OR PHYTIUM OR SD845 OR LX2160A)
+    set(PAGE16K OFF CACHE BOOL "")
+endif()
 if(M1 OR LARCH64)
-    set(LD80BITS OFF CACHE BOOL "")
+    set(PAGE16K ON CACHE BOOL "")
 endif()
 option(LD80BITS "Set to ON if host device have 80bits long double (i.e. i386)" ${LD80BITS})
 option(NOALIGN "Set to ON if host device doesn't need re-align (i.e. i386)" ${NOALIGN})