diff options
| author | Yang Liu <liuyang22@iscas.ac.cn> | 2025-07-30 14:33:23 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-30 08:33:23 +0200 |
| commit | f2baa6ed350362662482056312d20102b4c8c985 (patch) | |
| tree | f0327ca37d17ecfa72f2969b0cd358312ec2ffd5 | |
| parent | 5fd843750fe1af2b8775f0e491cd07d1cf06fe77 (diff) | |
| download | box64-f2baa6ed350362662482056312d20102b4c8c985.tar.gz box64-f2baa6ed350362662482056312d20102b4c8c985.zip | |
[RV64_DYNAREC] Added MMX handling to `fpu_{push,pop}cache` for vector (#2858)
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_helper.c | 33 |
1 files changed, 28 insertions, 5 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_helper.c b/src/dynarec/rv64/dynarec_rv64_helper.c index 8a21e80e..4c4c446f 100644 --- a/src/dynarec/rv64/dynarec_rv64_helper.c +++ b/src/dynarec/rv64/dynarec_rv64_helper.c @@ -2197,8 +2197,6 @@ void fpu_pushcache(dynarec_rv64_t* dyn, int ninst, int s1, int not07) } // for vector registers, we might lost all of them, that means for extcache, - // we're saving 0..15 (SSE). - // TODO: save MMX registers too when we add support for MMX vector. n = 0; for (int i = start; i < 16; i++) if (dyn->e.ssecache[i].v != -1 && dyn->e.ssecache[i].vector) ++n; @@ -2223,6 +2221,19 @@ void fpu_pushcache(dynarec_rv64_t* dyn, int ninst, int s1, int not07) } MESSAGE(LOG_DUMP, "\t------- Push (vector) XMM Cache (%d)\n", n); } + n = 0; + for (int i = 0; i < 8; ++i) + if (dyn->e.mmxcache[i].v != -1 && dyn->e.mmxcache[i].vector) ++n; + if (n) { + MESSAGE(LOG_DUMP, "\tPush (vector) MMX Cache (%d)------\n", n); + for (int i = 0; i < 8; ++i) + if (dyn->e.mmxcache[i].v != -1 && dyn->e.mmxcache[i].vector) { + SET_ELEMENT_WIDTH(s1, VECTOR_SEW64, 0); + VFMV_F_S(dyn->e.mmxcache[i].reg, dyn->e.mmxcache[i].reg); + FSD(dyn->e.mmxcache[i].reg, xEmu, offsetof(x64emu_t, mmx[i])); + } + MESSAGE(LOG_DUMP, "\t------- Push (vector) MMX Cache (%d)\n", n); + } } void fpu_popcache(dynarec_rv64_t* dyn, int ninst, int s1, int not07) { @@ -2248,7 +2259,7 @@ void fpu_popcache(dynarec_rv64_t* dyn, int ninst, int s1, int not07) for (int i = 18; i < 24; ++i) if (dyn->e.extcache[i].v != 0) ++n; if (n) { - MESSAGE(LOG_DUMP, "\tPush (float) x87/MMX Cache (%d)------\n", n); + MESSAGE(LOG_DUMP, "\tPop (float) x87/MMX Cache (%d)------\n", n); int p = 0; for (int i = 18; i < 24; ++i) if (dyn->e.extcache[i].v != 0) { @@ -2264,11 +2275,10 @@ void fpu_popcache(dynarec_rv64_t* dyn, int ninst, int s1, int not07) ++p; } ADDI(xSP, xSP, 8 * ((n + 1) & ~1)); - MESSAGE(LOG_DUMP, "\t------- Push (float) x87/MMX Cache (%d)\n", n); + MESSAGE(LOG_DUMP, "\t------- Pop (float) x87/MMX Cache (%d)\n", n); } // vector registers - // TODO: restore MMX registers too when we add support for MMX vector. n = 0; for (int i = start; i < 16; i++) if (dyn->e.ssecache[i].v != -1 && dyn->e.ssecache[i].vector) ++n; @@ -2284,6 +2294,19 @@ void fpu_popcache(dynarec_rv64_t* dyn, int ninst, int s1, int not07) } MESSAGE(LOG_DUMP, "\t------- Pop (vector) XMM Cache (%d)\n", n); } + n = 0; + for (int i = 0; i < 8; ++i) + if (dyn->e.mmxcache[i].v != -1 && dyn->e.mmxcache[i].vector) ++n; + if (n) { + MESSAGE(LOG_DUMP, "\tPop (vector) MMX Cache (%d)------\n", n); + for (int i = 0; i < 8; ++i) + if (dyn->e.mmxcache[i].v != -1 && dyn->e.mmxcache[i].vector) { + SET_ELEMENT_WIDTH(s1, VECTOR_SEW64, 0); + FLD(dyn->e.mmxcache[i].reg, xEmu, offsetof(x64emu_t, mmx[i])); + VFMV_S_F(dyn->e.mmxcache[i].reg, dyn->e.mmxcache[i].reg); + } + MESSAGE(LOG_DUMP, "\t------- Pop (vector) MMX Cache (%d)\n", n); + } } void fpu_purgecache(dynarec_rv64_t* dyn, int ninst, int next, int s1, int s2, int s3) |