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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-06-02 15:30:43 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-06-02 15:30:43 +0200 |
| commit | 3f3f8b41e9343bca279800a2f117e8405c67e86d (patch) | |
| tree | 04b2aea71a3712e5c18c2079781e1b1980813343 /src/dynarec/dynarec_arm64_db.c | |
| parent | d3ea3909830b837cb6aa0a3e74af72c10575f2f9 (diff) | |
| download | box64-3f3f8b41e9343bca279800a2f117e8405c67e86d.tar.gz box64-3f3f8b41e9343bca279800a2f117e8405c67e86d.zip | |
[DYNAREC] Fix x87opcode with rounding
Diffstat (limited to 'src/dynarec/dynarec_arm64_db.c')
| -rw-r--r-- | src/dynarec/dynarec_arm64_db.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/dynarec/dynarec_arm64_db.c b/src/dynarec/dynarec_arm64_db.c index a54296bb..11d5e45b 100644 --- a/src/dynarec/dynarec_arm64_db.c +++ b/src/dynarec/dynarec_arm64_db.c @@ -186,14 +186,14 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin FCVTZSwD(ed, s0); WBACK; #else - MSR_fpsr(x5); - BFCw(x5, FPSR_IOC, 1); // reset IOC bit MRS_fpsr(x5); + BFCw(x5, FPSR_IOC, 1); // reset IOC bit + MSR_fpsr(x5); FRINTZD(s0, v1); VFCVTZSd(s0, s0); SQXTN_S_D(s0, s0); VSTR32_U12(s0, wback, fixedaddress); - MSR_fpsr(x5); // get back FPSR to check the IOC bit + MRS_fpsr(x5); // get back FPSR to check the IOC bit TBZ_NEXT(x5, FPSR_IOC); MOV32w(x5, 0x80000000); STRw_U12(x5, wback, fixedaddress); @@ -217,14 +217,14 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin FCVTZSwD(ed, s0); WBACK; #else - MSR_fpsr(x5); - BFCw(x5, FPSR_IOC, 1); // reset IOC bit MRS_fpsr(x5); + BFCw(x5, FPSR_IOC, 1); // reset IOC bit + MSR_fpsr(x5); FRINTXD(s0, v1); VFCVTZSd(s0, s0); SQXTN_S_D(s0, s0); VSTR32_U12(s0, wback, fixedaddress); - MSR_fpsr(x5); // get back FPSR to check the IOC bit + MRS_fpsr(x5); // get back FPSR to check the IOC bit TBZ_NEXT(x5, FPSR_IOC); MOV32w(x5, 0x80000000); STRw_U12(x5, wback, fixedaddress); @@ -248,14 +248,14 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin FCVTZSwD(ed, s0); WBACK; #else - MSR_fpsr(x5); - BFCw(x5, FPSR_IOC, 1); // reset IOC bit MRS_fpsr(x5); + BFCw(x5, FPSR_IOC, 1); // reset IOC bit + MSR_fpsr(x5); FRINTXD(s0, v1); VFCVTZSd(s0, s0); SQXTN_S_D(s0, s0); VSTR32_U12(s0, wback, fixedaddress); - MSR_fpsr(x5); // get back FPSR to check the IOC bit + MRS_fpsr(x5); // get back FPSR to check the IOC bit TBZ_NEXT(x5, FPSR_IOC); MOV32w(x5, 0x80000000); STRw_U12(x5, wback, fixedaddress); |