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| author | ptitSeb <sebastien.chev@gmail.com> | 2023-04-28 12:32:17 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2023-04-28 12:32:26 +0200 |
| commit | 2ebde976db3337a0b78e1df0dd475c7bd5355511 (patch) | |
| tree | 5076d16f5b20e04076e23dba02f362bbc087a927 /src/dynarec | |
| parent | dbaee7c49ca20c9af0c0f3cabfe1ed1d72021610 (diff) | |
| download | box64-2ebde976db3337a0b78e1df0dd475c7bd5355511.tar.gz box64-2ebde976db3337a0b78e1df0dd475c7bd5355511.zip | |
Improved x87 FIST(T)(P) opcode ([ARM64_DYNAREC] too)
Diffstat (limited to 'src/dynarec')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_df.c | 41 |
1 files changed, 26 insertions, 15 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_df.c b/src/dynarec/arm64/dynarec_arm64_df.c index c9a6a9f6..5c3ee841 100644 --- a/src/dynarec/arm64/dynarec_arm64_df.c +++ b/src/dynarec/arm64/dynarec_arm64_df.c @@ -178,6 +178,7 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin #else MRS_fpsr(x5); BFCw(x5, FPSR_IOC, 1); // reset IOC bit + BFCw(x5, FPSR_QC, 1); // reset QC bit MSR_fpsr(x5); if(ST_IS_F(0)) { VFCVTZSs(s0, v1); @@ -185,13 +186,16 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin VFCVTZSd(s0, v1); SQXTN_S_D(s0, s0); } - SQXTN_H_S(s0, s0); - VST16(s0, wback, fixedaddress); + VMOVSto(x3, s0, 0); MRS_fpsr(x5); // get back FPSR to check the IOC bit - TBZ_MARK3(x5, FPSR_IOC); - MOV32w(x5, 0x8000); - STH(x5, wback, fixedaddress); + TBNZ_MARK2(x5, FPSR_IOC); + SXTHw(x5, x3); // check if 16bits value is fine + SUBw_REG(x5, x5, x3); + CBZw_MARK3(x5); + MARK2; + MOV32w(x3, 0x8000); MARK3; + STH(x3, wback, fixedaddress); #endif x87_do_pop(dyn, ninst, x3); break; @@ -212,6 +216,7 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin #else MRS_fpsr(x5); BFCw(x5, FPSR_IOC, 1); // reset IOC bit + BFCw(x5, FPSR_QC, 1); // reset QC bit MSR_fpsr(x5); if(ST_IS_F(0)) { FRINTXS(s0, v1); @@ -221,13 +226,16 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin VFCVTZSd(s0, s0); SQXTN_S_D(s0, s0); } - SQXTN_H_S(s0, s0); - VST16(s0, wback, fixedaddress); + VMOVSto(x3, s0, 0); MRS_fpsr(x5); // get back FPSR to check the IOC bit - TBZ_MARK3(x5, FPSR_IOC); - MOV32w(x5, 0x8000); - STH(x5, wback, fixedaddress); + TBNZ_MARK2(x5, FPSR_IOC); + SXTHw(x5, x3); // check if 16bits value is fine + SUBw_REG(x5, x5, x3); + CBZw_MARK3(x5); + MARK2; + MOV32w(x3, 0x8000); MARK3; + STH(x3, wback, fixedaddress); #endif x87_restoreround(dyn, ninst, u8); break; @@ -257,13 +265,16 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin VFCVTZSd(s0, s0); SQXTN_S_D(s0, s0); } - SQXTN_H_S(s0, s0); - VST16(s0, wback, fixedaddress); + VMOVSto(x3, s0, 0); MRS_fpsr(x5); // get back FPSR to check the IOC bit - TBZ_MARK3(x5, FPSR_IOC); - MOV32w(x5, 0x8000); - STH(x5, wback, fixedaddress); + TBNZ_MARK2(x5, FPSR_IOC); + SXTHw(x5, x3); // check if 16bits value is fine + SUBw_REG(x5, x5, x3); + CBZw_MARK3(x5); + MARK2; + MOV32w(x3, 0x8000); MARK3; + STH(x3, wback, fixedaddress); #endif x87_do_pop(dyn, ninst, x3); x87_restoreround(dyn, ninst, u8); |