More cases to test17, and added -NAN generation to divpd ([DYNAREC] too)

1 files changed, 15 insertions, 2 deletions

diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c
index abd12c04..b90c27cb 100755
--- a/src/dynarec/arm64/dynarec_arm64_660f.c
+++ b/src/dynarec/arm64/dynarec_arm64_660f.c
@@ -769,8 +769,21 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("DIVPD Gx, Ex");

             nextop = F8;

             GETEX(q0, 0);

-            GETGX(v0);

-            VFDIVQD(v0, v0, q0);

+            GETGX(q1);

+            if(!box64_dynarec_fastnan) {

+                v0 = fpu_get_scratch(dyn);

+                v1 = fpu_get_scratch(dyn);

+                // check if any input value was NAN

+                VFMAXQD(v0, q0, q1);    // propagate NAN

+                FCMEQQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN

+            }

+            VFDIVQD(q1, q1, q0);

+            if(!box64_dynarec_fastnan) {

+                FCMEQQD(v1, q1, q1);    // 0 => out is NAN

+                VBICQ(v1, v0, v1);      // forget it in any input was a NAN already

+                VSHLQ_64(v1, v1, 63);   // only keep the sign bit

+                VORRQ(q1, q1, v1);      // NAN -> -NAN

+            }

             break;

         case 0x5F:

             INST_NAME("MAXPD Gx, Ex");