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authorptitSeb <sebastien.chev@gmail.com>2024-06-24 17:34:02 +0200
committerptitSeb <sebastien.chev@gmail.com>2024-06-24 17:34:02 +0200
commit579ae99d1b96f44709a4b4396d59d3e15bda26f7 (patch)
treec1bed6fe2c904d7f4b711bc4d6ad49d5fdefe209 /src/dynarec
parentfa702c0240d0741def3955697067b562cc7a7fcd (diff)
downloadbox64-579ae99d1b96f44709a4b4396d59d3e15bda26f7.tar.gz
box64-579ae99d1b96f44709a4b4396d59d3e15bda26f7.zip
[ARM64_DYNAREC] Added 0F C7 /6 opcode, with hardware support if present
Diffstat (limited to 'src/dynarec')
-rw-r--r--src/dynarec/arm64/arm64_emitter.h2
-rw-r--r--src/dynarec/arm64/dynarec_arm64_0f.c19
2 files changed, 21 insertions, 0 deletions
diff --git a/src/dynarec/arm64/arm64_emitter.h b/src/dynarec/arm64/arm64_emitter.h
index f0d4c4b8..69871657 100644
--- a/src/dynarec/arm64/arm64_emitter.h
+++ b/src/dynarec/arm64/arm64_emitter.h
@@ -784,6 +784,8 @@ int convert_bitmask(uint64_t bitmask);
 #define MRS_cntvct_el0(Rt)              EMIT(MRS_gen(1, 1, 0b011, 0b1110, 0b0000, 0b010, Rt))
 // mrs   x0, cntpctss_el0     op0=0b11 op1=0b011 CRn=0b1110 CRm=0b0000 op2=0b101
 #define MRS_cntpctss_el0(Rt)            EMIT(MRS_gen(1, 1, 0b011, 0b1110, 0b0000, 0b101, Rt))
+// mrs   rt, rndr           op0=0b11	op1=0b011	CRn=0b0010	CRm=0b0100	op2=0b000
+#define MRS_rndr(Rt)                    EMIT(MRS_gen(1, 1, 0b011, 0b0010, 0b0100, 0b000, Rt))
 // NEON Saturation Bit
 #define FPSR_QC 27
 // NEON Input Denormal Cumulative
diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c
index 545a9554..8544d805 100644
--- a/src/dynarec/arm64/dynarec_arm64_0f.c
+++ b/src/dynarec/arm64/dynarec_arm64_0f.c
@@ -2369,6 +2369,25 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 FAKEED;

                 UDF(0);

                 break;

+            case 6:

+                INST_NAME("RNDR Ed");

+                SETFLAGS(X_ALL, SF_SET_DF);

+                SET_DFNONE(x1);

+                IFX(F_OF|F_SF|F_ZF|F_PF|F_AF) {

+                    MOV32w(x1, (1<<F_OF)|(1<<F_SF)|(1<<F_ZF)|(1<<F_PF)|(1<<F_AF));

+                    BICw(xFlags, xFlags, x1);

+                }

+                if(arm64_rndr) {

+                    MRS_rndr(x1);

+                    IFX(X_CF) { CSETw(x3, cNE); }

+                } else {

+                    CALL(rex.w?((void*)get_random64):((void*)get_random32), x1);

+                    IFX(X_CF) { MOV32w(x3, 1); }

+                }

+                IFX(X_CF) { BFIw(xFlags, x3, F_CF, 1); }

+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0);

+                STxw(x1, wback, fixedaddress);

+                break;

             default:

                 DEFAULT;

             }